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Experimental FPU support for ARMv8-M. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13503 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-04-02 12:54:33 +00:00
parent f5975693b2
commit adadec5630
5 changed files with 61 additions and 11 deletions
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2
demos/STM32/RT-STM32L4R9-DISCOVERY/Makefile
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@ -66,7 +66,7 @@ endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
USE_FPU = hard
endif
# FPU-related options.

2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/Makefile
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@ -66,7 +66,7 @@ endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
USE_FPU = hard
endif
# FPU-related options.

2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
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File diff suppressed because one or more lines are too long

38
os/common/ports/ARMv8-M-ML/chcore.h
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@ -263,6 +263,26 @@ struct port_intctx {
uint32_t lr_thd;
uint32_t pc;
uint32_t xpsr;
#if (CORTEX_USE_FPU == TRUE) || defined(__DOXYGEN__)
uint32_t s0;
uint32_t s1;
uint32_t s2;
uint32_t s3;
uint32_t s4;
uint32_t s5;
uint32_t s6;
uint32_t s7;
uint32_t s8;
uint32_t s9;
uint32_t s10;
uint32_t s11;
uint32_t s12;
uint32_t s13;
uint32_t s14;
uint32_t s15;
uint32_t fpscr;
uint32_t reserved;
#endif /* CORTEX_USE_FPU == TRUE */
};
/**
@ -286,6 +306,24 @@ struct port_context {
uint32_t splim;
#endif
uint32_t lr_exc;
#if (CORTEX_USE_FPU == TRUE) || defined(__DOXYGEN__)
uint32_t s16;
uint32_t s17;
uint32_t s18;
uint32_t s19;
uint32_t s20;
uint32_t s21;
uint32_t s22;
uint32_t s23;
uint32_t s24;
uint32_t s25;
uint32_t s26;
uint32_t s27;
uint32_t s28;
uint32_t s29;
uint32_t s30;
uint32_t s31;
#endif /* CORTEX_USE_FPU == TRUE */
};
#endif /* !defined(_FROM_ASM_) */

28
os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
View File

@ -91,21 +91,27 @@ SVC_Handler:
// movs r3, #(2 << 5)
#if CH_DBG_ENABLE_STACK_CHECK
mrs r12, PSPLIM
stmia r1, {r2-r12,lr}
stmia r1!, {r2-r12,lr}
#else
stmia r1, {r2-r11,lr}
stmia r1!, {r2-r11,lr}
#endif
#if CORTEX_USE_FPU
vstmia r1, {s16-s31}
#endif
/* Restoring calle context of thread being swapped in.*/
adds r0, #CONTEXT_OFFSET
#if CH_DBG_ENABLE_STACK_CHECK
ldmia r0, {r2-r12, lr}
ldmia r0!, {r2-r12, lr}
msr PSPLIM, r12
#else
ldmia r0, {r2-r11, lr}
ldmia r0!, {r2-r11, lr}
#endif
msr BASEPRI, r3
msr PSP, r2
#if CORTEX_USE_FPU
vldmia r0, {s16-s31}
#endif
bx lr
/*--------------------------------------------------------------------------*
@ -124,9 +130,12 @@ PendSV_Handler:
mrs r3, BASEPRI
#if CH_DBG_ENABLE_STACK_CHECK
mrs r12, PSPLIM
stmia r1, {r2-r12,lr}
stmia r1!, {r2-r12,lr}
#else
stmia r1, {r2-r11,lr}
stmia r1!, {r2-r11,lr}
#endif
#if CORTEX_USE_FPU
vstmia r1, {s16-s31}
#endif
/* Selecting the thread to be swapped in.*/
@ -135,13 +144,16 @@ PendSV_Handler:
/* Restoring calle context of thread being swapped in.*/
adds r0, #CONTEXT_OFFSET
#if CH_DBG_ENABLE_STACK_CHECK
ldmia r0, {r2-r12, lr}
ldmia r0!, {r2-r12, lr}
msr PSPLIM, r12
#else
ldmia r0, {r2-r11, lr}
ldmia r0!, {r2-r11, lr}
#endif
msr BASEPRI, r3
msr PSP, r2
#if CORTEX_USE_FPU
vldmia r0, {s16-s31}
#endif
bx lr
/*--------------------------------------------------------------------------*