From b34bcc558b944c4e46892b6f71c1a213a82a91a2 Mon Sep 17 00:00:00 2001 From: vrepetenko Date: Sun, 25 Apr 2021 08:46:32 +0000 Subject: [PATCH] STM32 RCCv1: bd, hse32, pll_v2, ahb2 added. apb2 typo fixed. msi workaroud for undefined RCC_CFGR_SWS_MSI added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14317 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/LLD/RCCv1/stm32_ahb3.inc | 134 +++++++ os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc | 4 +- os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc | 92 +++++ os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc | 116 ++++++ os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc | 4 + os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc | 359 ++++++++++++++++++ 6 files changed, 707 insertions(+), 2 deletions(-) create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_ahb3.inc create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc create mode 100644 os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb3.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb3.inc new file mode 100644 index 000000000..1415a8756 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb3.inc @@ -0,0 +1,134 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_ahb3.inc + * @brief Shared AHB3 clock handler. + * + * @addtogroup STM32_AHB3_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @name SHDHPRE field bits definitions + * @{ + */ +#define STM32_SHDHPRE_MASK (15U << RCC_EXTCFGR_SHDHPRE_Pos) +#define STM32_SHDHPRE_FIELD(n) ((n) << RCC_EXTCFGR_SHDHPRE_Pos) +#define STM32_SHDHPRE_DIV1 STM32_SHDHPRE_FIELD(0U) +#define STM32_SHDHPRE_DIV2 STM32_SHDHPRE_FIELD(8U) +#define STM32_SHDHPRE_DIV3 STM32_SHDHPRE_FIELD(1U) +#define STM32_SHDHPRE_DIV4 STM32_SHDHPRE_FIELD(9U) +#define STM32_SHDHPRE_DIV5 STM32_SHDHPRE_FIELD(2U) +#define STM32_SHDHPRE_DIV6 STM32_SHDHPRE_FIELD(5U) +#define STM32_SHDHPRE_DIV8 STM32_SHDHPRE_FIELD(10U) +#define STM32_SHDHPRE_DIV10 STM32_SHDHPRE_FIELD(6U) +#define STM32_SHDHPRE_DIV16 STM32_SHDHPRE_FIELD(11U) +#define STM32_SHDHPRE_DIV32 STM32_SHDHPRE_FIELD(7U) +#define STM32_SHDHPRE_DIV64 STM32_SHDHPRE_FIELD(12U) +#define STM32_SHDHPRE_DIV128 STM32_SHDHPRE_FIELD(13U) +#define STM32_SHDHPRE_DIV256 STM32_SHDHPRE_FIELD(14U) +#define STM32_SHDHPRE_DIV512 STM32_SHDHPRE_FIELD(15U) + +#define STM32_SHDHPREF_MASK (1U << RCC_EXTCFGR_SHDHPREF_Pos) + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ + +/* Checks on configurations.*/ +#if !defined(STM32_SHDHPRE) +#error "STM32_SHDHPRE not defined in mcuconf.h" +#endif + +/** + * @brief AHB3 HCLK3/PCLK3 frequency. + */ +#if (STM32_SHDHPRE == STM32_SHDHPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK3 (STM32_SYSCLK / 1) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV2 +#define STM32_HCLK3 (STM32_SYSCLK / 2) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV4 +#define STM32_HCLK3 (STM32_SYSCLK / 3) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV4 +#define STM32_HCLK3 (STM32_SYSCLK / 4) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV5 +#define STM32_HCLK3 (STM32_SYSCLK / 5) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV6 +#define STM32_HCLK3 (STM32_SYSCLK / 6) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV8 +#define STM32_HCLK3 (STM32_SYSCLK / 8) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV10 +#define STM32_HCLK3 (STM32_SYSCLK / 10) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV16 +#define STM32_HCLK3 (STM32_SYSCLK / 16) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV32 +#define STM32_HCLK3 (STM32_SYSCLK / 32) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV64 +#define STM32_HCLK3 (STM32_SYSCLK / 64) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV128 +#define STM32_HCLK3 (STM32_SYSCLK / 128) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV256 +#define STM32_HCLK3 (STM32_SYSCLK / 256) + +#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV512 +#define STM32_HCLK3 (STM32_SYSCLK / 512) + +#else +#error "invalid STM32_SHDHPRE value specified" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc index eeb96e1e2..a6285f663 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc @@ -46,8 +46,8 @@ /* Registry checks for robustness.*/ /* Checks on configurations.*/ -#if !defined(STM32_PPRE1) -#error "STM32_PPRE1 not defined in mcuconf.h" +#if !defined(STM32_PPRE2) +#error "STM32_PPRE2 not defined in mcuconf.h" #endif /* Input checks.*/ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc new file mode 100644 index 000000000..b48e4c968 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc @@ -0,0 +1,92 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_bd.inc + * @brief Shared backup domain handler. + * + * @addtogroup STM32_BD_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + */ +static inline void bd_init(void) { + uint32_t bdcr; + + /* Current settings.*/ + bdcr = RCC->BDCR; + +#if HAL_USE_RTC + /* RTC enable.*/ + if ((bdcr & RCC_BDCR_RTCEN) == 0U) { + bdcr |= RCC_BDCR_RTCEN; + } +#endif + + /* Selectors.*/ + bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK); + bdcr |= STM32_RTCSEL | STM32_LSCOSEL; + + /* Final settings.*/ + RCC->BDCR = bdcr; +} + +/** + * @brief Resets the backup domain. + * @note WARNING! Changing RTC clock source impossible without reset + * of the whole BKP domain. + */ +static inline void bd_reset(void) { + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0U; + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc new file mode 100644 index 000000000..686f32905 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc @@ -0,0 +1,116 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_hse32.inc + * @brief Shared HSE32 clock handler. + * + * @addtogroup STM32_HSE32_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief HSE32 clock frequency. + */ +#define STM32_HSI32CLK 32000000 + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_HSE32) +#error "STM32_RCC_HAS_HSE32 not defined in stm32_registry.h" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_HSE32_ENABLED) +#error "STM32_HSE32_ENABLED not defined in mcuconf.h" +#endif + +#if defined(STM32_HSECLK) +#error "STM32_HSECLK should not be defined in board.h" +#endif + +#if defined(STM32_HSE_ENABLED) +#error "STM32_HSE_ENABLED should not be defined in mcuconf.h" +#endif + +#if STM32_HSE32_ENABLED + +/* HSE clock frequency.*/ +#if STM32_HSE32PRE == STM32_HSE32PRE_DIV1 +#define STM32_HSECLK STM32_HSE32CLK +#elif STM32_HSE32PRE == STM32_HSE32PRE_DIV2 +#define STM32_HSECLK (STM32_HSE32CLK / 2) +#else +#error "invalid STM32_HSE32PRE value specified" +#endif + +#if !defined(STM32_HSE32SRC) || \ + (STM32_HSE32SRC != STM32_HSE32_XTAL && \ + STM32_HSE32SRC != STM32_HSE32_TCXO && \ + STM32_HSE32SRC != STM32_HSE32_EXTS) +#error "STM32_HSE32SRC should by defined in mcuconf.h with correct value" +#endif + +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void hse32_init(void) { + +#if STM32_HSE32_ENABLED + +#if STM32_HSE32SRC == STM32_HSE32_TCXO + /* Enable PB0-VDDTCXO.*/ + RCC->CR |= RCC_CR_HSEBYPPWR; +#endif /* STM32_HSESRC == STM32_HSE_TCXO */ + + /* Set HSE32 SYSCLK prescaler.*/ + RCC->CR |= STM32_HSE32PRE; + + /* HSE32 activation.*/ + RCC->CR |= RCC_CR_HSEON; + + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Wait until HSE32 is stable. */ +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc index f987314a2..7a80a1258 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc @@ -148,6 +148,10 @@ #error "invalid STM32_MSISRANGE value specified" #endif +#if !defined(RCC_CFGR_SWS_MSI) +#define RCC_CFGR_SWS_MSI 0U +#endif + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc new file mode 100644 index 000000000..32e942ea7 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc @@ -0,0 +1,359 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_pll_v2.inc + * @brief Shared PLL handler v2. + * + * @addtogroup STM32_PLL_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ + +#if !defined(STM32_RCC_HAS_PLL) +#define STM32_RCC_HAS_PLL FALSE +#endif + +#if STM32_RCC_HAS_PLL + +/* Checks on configurations.*/ +#if !defined(STM32_PLLSRC) +#error "STM32_PLLSRC not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLLM_VALUE) +#error "STM32_PLLM_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLLN_VALUE) +#error "STM32_PLLN_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL_HAS_P && !defined(STM32_PLLP_VALUE) +#error "STM32_PLLP_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL_HAS_Q && !defined(STM32_PLLQ_VALUE) +#error "STM32_PLLQ_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL_HAS_R && !defined(STM32_PLLR_VALUE) +#error "STM32_PLLR_VALUE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PLLN_VALUE_MAX) +#error "STM32_PLLN_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLN_VALUE_MIN) +#error "STM32_PLLN_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLM_VALUE_MAX) +#error "STM32_PLLM_VALUE_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLM_VALUE_MIN) +#error "STM32_PLLM_VALUE_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_R && !defined(STM32_PLLR_VALUE_MAX) +#error "STM32_PLLR_VALUE_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_R && !defined(STM32_PLLR_VALUE_MIN) +#error "STM32_PLLR_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !STM32_RCC_PLL_HAS_Q && defined(STM32_PLLQ_VALUE_MAX) +#error "STM32_PLLQ_VALUE_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_Q && !defined(STM32_PLLQ_VALUE_MIN) +#error "STM32_PLLQ_VALUE_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_P && !defined(STM32_PLLP_VALUE_MAX) +#error "STM32_PLLP_VALUE_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_P && !defined(STM32_PLLP_VALUE_MIN) +#error "STM32_PLLP_VALUE_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLIN_MAX) +#error "STM32_PLLIN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLIN_MIN) +#error "STM32_PLLIN_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLVCO_MAX) +#error "STM32_PLLIN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLVCO_MIN) +#error "STM32_PLLIN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLP_MAX) +#error "STM32_PLLP_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLP_MIN) +#error "STM32_PLLP_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLQ_MAX) +#error "STM32_PLLQ_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLQ_MIN) +#error "STM32_PLLQ_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLR_MAX) +#error "STM32_PLLR_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLLR_MIN) +#error "STM32_PLLR_MIN not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_ACTIVATE_PLL) +#error "STM32_ACTIVATE_PLL not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_P && !defined(STM32_PLLPEN) +#error "STM32_PLLPEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_Q && !defined(STM32_PLLQEN) +#error "STM32_PLLQEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL_HAS_R && !defined(STM32_PLLREN) +#error "STM32_PLLREN not defined in hal_lld.h" +#endif + +#if STM32_ACTIVATE_PLL && (STM32_PLLCLKIN == 0) +#error "PLL activation required but no PLL clock selected" +#endif + +#if (STM32_PLLCLKIN != 0) && \ + ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= STM32_PLLM_VALUE_MIN) && (STM32_PLLM_VALUE <= STM32_PLLM_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4) +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief STM32_PLLN field. + */ +#if ((STM32_PLLN_VALUE >= STM32_PLLN_VALUE_MIN) && \ + (STM32_PLLN_VALUE <= STM32_PLLN_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLLN (STM32_PLLN_VALUE << 8) +#else +#error "invalid STM32_PLLN_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) + +/* + * PLL VCO frequency range check. + */ +#if STM32_ACTIVATE_PLL && \ + ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/*---------------------------------------------------------------------------*/ +/* P output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL_HAS_P || defined(__DOXYGEN__) +/** + * @brief STM32_PLLP field. + */ +#if ((STM32_PLLP_VALUE_MIN >= STM32_PLLP_VALUE_MIN) && (STM32_PLLP_VALUE_MAX <= 32)) || \ + defined(__DOXYGEN__) +#define STM32_PLLP ((STM32_PLLP_VALUE - 1) << 17) +#else +#error "invalid STM32_PLLP_VALUE value specified" +#endif + +/** + * @brief PLL P output clock frequency. + */ +#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) + +/* + * PLL-P output frequency range check. + */ +#if STM32_ACTIVATE_PLL && \ + ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX)) +#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" +#endif + +#else /* !STM32_RCC_PLL_HAS_P */ +#define STM32_PLLP 0 +#define STM32_PLLPEN 0 +#endif /* !STM32_RCC_PLL_HAS_P */ + +/*---------------------------------------------------------------------------*/ +/* Q output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL_HAS_Q || defined(__DOXYGEN__) + +/** + * @brief STM32_PLLQ field. + */ +#if ((STM32_PLLQ_VALUE >= STM32_PLLQ_VALUE_MIN) && (STM32_PLLQ_VALUE <= STM32_PLLQ_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLLQ ((STM32_PLLQ_VALUE - 1) << 25) +#else +#error "invalid STM32_PLLQ_VALUE value specified" +#endif + +/** + * @brief PLL Q output clock frequency. + */ +#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE) + +/* + * PLL-Q output frequency range check. + */ +#if STM32_ACTIVATE_PLL && \ + ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX)) +#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" +#endif + +/** + * @brief PLL Q output clock frequency. + */ +#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE) + +#else /* !STM32_RCC_PLL_HAS_Q */ +#define STM32_PLLQ 0 +#define STM32_PLLQEN 0 +#endif /* !STM32_RCC_PLL_HAS_Q */ + +/*---------------------------------------------------------------------------*/ +/* R output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL_HAS_R || defined(__DOXYGEN__) + +/** + * @brief STM32_PLLR field. + */ +#if ((STM32_PLLR_VALUE >= STM32_PLLR_VALUE_MIN) && (STM32_PLLR_VALUE <= STM32_PLLP_VALUE_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLLR ((STM32_PLLR_VALUE - 1) << 29) +#else +#error "invalid STM32_PLLR_VALUE value specified" +#endif + +/** + * @brief PLL R output clock frequency. + */ +#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE) + +/* + * PLL-R output frequency range check. + */ +#if STM32_ACTIVATE_PLL && \ + ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX)) +#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" +#endif + +#else /* !STM32_RCC_PLL_HAS_R */ +#define STM32_PLLR 0 +#define STM32_PLLREN 0 +#endif /* !STM32_RCC_PLL_HAS_R */ + +//// old + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void pll_init(void) { + +#if STM32_ACTIVATE_PLL + /* PLLM and PLLSRC are common to all PLLs.*/ + RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN | + STM32_PLLQ | STM32_PLLQEN | + STM32_PLLP | STM32_PLLPEN | + STM32_PLLN | STM32_PLLM | + STM32_PLLSRC; + + /* PLL activation.*/ + RCC->CR |= RCC_CR_PLLON; + + /* Waiting for PLL lock.*/ + while ((RCC->CR & RCC_CR_PLLRDY) == 0) + ; +#endif +} + +static inline void pll_deinit(void) { + + /* PLL de-activation.*/ + RCC->PLLCFGR &= ~RCC_CR_PLLON; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#endif /* STM32_RCC_HAS_PLL */ + +/** @} */