mirror of https://github.com/rusefi/ChibiOS.git
More ADCv5 fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15740 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -98,7 +98,7 @@ static void adc_lld_stop_adc(ADC_TypeDef *adc) {
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/* Disabling the ADC.*/
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/* Disabling the ADC.*/
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adc->CR |= ADC_CR_ADDIS;
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adc->CR |= ADC_CR_ADDIS;
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while ((adc->CR & ADC_CR_ADDIS) != 0U) {
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while ((adc->CR & ADC_CR_ADEN) != 0U) {
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/* Waiting for ADC to be disabled.*/
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/* Waiting for ADC to be disabled.*/
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}
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}
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}
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}
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@ -238,26 +238,28 @@ void adc_lld_start(ADCDriver *adcp) {
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*/
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock and analog part.*/
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/* If in ready state then disables the ADC peripheral and clock.*/
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if (adcp->state == ADC_READY) {
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if (adcp->state == ADC_READY) {
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dmaStreamFreeI(adcp->dmastp);
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dmaStreamFreeI(adcp->dmastp);
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adcp->dmastp = NULL;
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adcp->dmastp = NULL;
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/* Disabling the ADC.*/
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adcp->adc->CR |= ADC_CR_ADDIS;
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while ((adcp->adc->CR & ADC_CR_ADEN) != 0U) {
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/* Waiting for ADC to be disabled.*/
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}
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/* Regulator off.*/
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/* Regulator off.*/
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#if defined(ADC_CR_ADVREGEN)
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#if defined(ADC_CR_ADVREGEN)
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adcp->adc->CR &= ~ADC_CR_ADVREGEN;
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adcp->adc->CR &= ~ADC_CR_ADVREGEN;
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#endif
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#endif
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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rccDisableADC1();
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#endif
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}
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/* Disabling the ADC.*/
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#if STM32_ADC_USE_ADC1
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adcp->adc->CR |= ADC_CR_ADDIS;
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if (&ADCD1 == adcp) {
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while ((adcp->adc->CR & ADC_CR_ADDIS) != 0U) {
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rccDisableADC1();
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/* Waiting for ADC to be disabled.*/
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}
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#endif
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}
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}
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}
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}
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@ -269,6 +271,7 @@ void adc_lld_stop(ADCDriver *adcp) {
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* @notapi
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* @notapi
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*/
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t mode, cfgr1, cfgr2;
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uint32_t mode, cfgr1, cfgr2;
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const ADCConversionGroup *grpp = adcp->grpp;
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const ADCConversionGroup *grpp = adcp->grpp;
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@ -322,7 +325,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
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/* Enable the ADC. Note: Setting ADEN must be deferred as a STM32G071 will
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/* Enable the ADC. Note: Setting ADEN must be deferred as a STM32G071 will
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reset RES[1:0] resolution bits if CFGR1 is modified with ADEN set
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reset RES[1:0] resolution bits if CFGR1 is modified with ADEN set
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(see STM32G071xx errata ES0418 Rev 3 2.6.2). Same applies to STM32WLE.*/
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(see STM32G071xx errata ES0418 Rev 3 2.6.2). Same applies to STM32WL.*/
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adcp->adc->CR |= ADC_CR_ADEN;
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adcp->adc->CR |= ADC_CR_ADEN;
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while ((adcp->adc->ISR & ADC_ISR_ADRDY) == 0U) {
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while ((adcp->adc->ISR & ADC_ISR_ADRDY) == 0U) {
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/* Wait for the ADC to become ready.*/
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/* Wait for the ADC to become ready.*/
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