From b4e1ecc760fb1dea0089428a4ba4cdd9510e1cdb Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 11 Jan 2017 10:32:33 +0000 Subject: [PATCH] Various STM32 timers-related fixes into registry and RCC files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10030 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 28 +- os/hal/ports/STM32/STM32F1xx/stm32_rcc.h | 247 ++++++++++++++++++ os/hal/ports/STM32/STM32F1xx/stm32_registry.h | 42 +-- os/hal/ports/STM32/STM32F37x/stm32_rcc.h | 154 ++++++++++- os/hal/ports/STM32/STM32F37x/stm32_registry.h | 16 +- os/hal/ports/STM32/STM32F3xx/stm32_rcc.h | 100 +++++++ os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 4 +- os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 40 +-- os/hal/ports/STM32/STM32F7xx/stm32_registry.h | 12 +- 9 files changed, 560 insertions(+), 83 deletions(-) diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index 028ac219b..2f6f8224c 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -499,11 +499,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -709,11 +709,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -933,11 +933,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -1174,11 +1174,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -1416,11 +1416,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM2 FALSE #define STM32_HAS_TIM4 FALSE @@ -1682,11 +1682,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -1966,11 +1966,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h index b14261d3a..6abb74876 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h @@ -876,6 +876,253 @@ * @api */ #define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) + +/** + + * @brief Enables the TIM9 peripheral clock. + + * @note The @p lp parameter is ignored in this family. + + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Disables the TIM9 peripheral clock. + + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Resets the TIM9 peripheral. + * + * @api + */ +#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) + +/** + * @brief Enables the TIM10 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp) + +/** + * @brief Disables the TIM10 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp) + +/** + * @brief Resets the TIM10 peripheral. + * + * @api + */ +#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST) + +/** + * @brief Enables the TIM11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Disables the TIM11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Resets the TIM11 peripheral. + * + * @api + */ +#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) + +/** + * @brief Enables the TIM12 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Disables the TIM12 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Resets the TIM12 peripheral. + * + * @api + */ +#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) + +/** + * @brief Enables the TIM13 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Disables the TIM13 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Resets the TIM13 peripheral. + * + * @api + */ +#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) + +/** + * @brief Enables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) + +/** + * @brief Enables the TIM15 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Disables the TIM15 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Resets the TIM15 peripheral. + * + * @api + */ +#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST) /** @} */ /** diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h index e1e3d5e8e..e8d19a246 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h @@ -199,11 +199,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM8 FALSE @@ -800,30 +800,12 @@ #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 4 -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM12 TRUE -#define STM32_TIM12_IS_32BITS FALSE -#define STM32_TIM12_CHANNELS 2 - -#define STM32_HAS_TIM13 TRUE -#define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 - -#define STM32_HAS_TIM14 TRUE -#define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 - +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE @@ -1056,11 +1038,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -1068,11 +1050,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE diff --git a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h index 716b64e89..5310ab103 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h @@ -709,7 +709,6 @@ * @api */ #define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) -/** @} */ /** * @brief Enables the TIM7 peripheral clock. @@ -735,7 +734,6 @@ * @api */ #define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) -/** @} */ /** * @brief Enables the TIM12 peripheral clock. @@ -761,7 +759,32 @@ * @api */ #define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) -/** @} */ + +/** + * @brief Enables the TIM13 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Disables the TIM13 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Resets the TIM13 peripheral. + * + * @api + */ +#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) + /** * @brief Enables the TIM14 peripheral clock. @@ -787,6 +810,131 @@ * @api */ #define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) + +/** + * @brief Enables the TIM15 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Disables the TIM15 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Resets the TIM15 peripheral. + * + * @api + */ +#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST) + +/** + * @brief Enables the TIM18 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM18(lp) rccEnableAPB1(RCC_APB1ENR_TIM18EN, lp) + +/** + * @brief Disables the TIM18 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM18(lp) rccDisableAPB1(RCC_APB1ENR_TIM18EN, lp) + +/** + * @brief Resets the TIM18 peripheral. + * + * @api + */ +#define rccResetTIM18() rccResetAPB1(RCC_APB1RSTR_TIM18RST) + +/** + * @brief Enables the TIM19 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM19(lp) rccEnableAPB2(RCC_APB2ENR_TIM19EN, lp) + +/** + * @brief Disables the TIM19 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM19(lp) rccDisableAPB2(RCC_APB2ENR_TIM19EN, lp) + +/** + * @brief Resets the TIM19 peripheral. + * + * @api + */ +#define rccResetTIM19() rccResetAPB2(RCC_APB2RSTR_TIM19RST) /** @} */ /** diff --git a/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/os/hal/ports/STM32/STM32F37x/stm32_registry.h index 3f22e5c79..55ba86766 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_registry.h @@ -204,11 +204,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE @@ -216,11 +216,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM18 TRUE #define STM32_TIM18_IS_32BITS FALSE @@ -456,11 +456,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE @@ -468,11 +468,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM18 TRUE #define STM32_TIM18_IS_32BITS FALSE diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h index 9b92679e0..0455380fb 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h @@ -732,6 +732,106 @@ * @api */ #define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) + +/** + * @brief Enables the TIM15 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Disables the TIM15 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Resets the TIM15 peripheral. + * + * @api + */ +#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST) + +/** + * @brief Enables the TIM20 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp) + +/** + * @brief Disables the TIM20 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM20(lp) rccDisableAPB2(RCC_APB2ENR_TIM20EN, lp) + +/** + * @brief Resets the TIM20 peripheral. + * + * @api + */ +#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST) /** @} */ /** diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index 3e3da573e..e1bf383bf 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -517,7 +517,7 @@ #define STM32_HAS_TIM20 TRUE #define STM32_TIM20_IS_32BITS FALSE -#define STM32_TIM20_CHANNELS 4 +#define STM32_TIM20_CHANNELS 6 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM9 FALSE @@ -2838,7 +2838,7 @@ #define STM32_HAS_TIM20 TRUE #define STM32_TIM20_IS_32BITS FALSE -#define STM32_TIM20_CHANNELS 4 +#define STM32_TIM20_CHANNELS 6 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM9 FALSE diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 25be1e4ed..941deffd7 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -686,7 +686,7 @@ #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 +#define STM32_TIM8_CHANNELS 4 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE @@ -694,11 +694,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -706,11 +706,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -1043,7 +1043,7 @@ #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 +#define STM32_TIM8_CHANNELS 4 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE @@ -1051,11 +1051,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -1063,11 +1063,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -1398,11 +1398,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -1705,11 +1705,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE @@ -2293,11 +2293,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -2305,11 +2305,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -2611,11 +2611,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h index abcafeb66..62212781f 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h @@ -301,11 +301,11 @@ #define STM32_SPI6_TX_DMA_CHN 0x00100000 /* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 +#define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_CHANNELS 6 #define STM32_TIM1_UP_HANDLER VectorA4 #define STM32_TIM1_CC_HANDLER VectorAC #define STM32_TIM1_UP_NUMBER 25 @@ -363,13 +363,13 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */ #define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */ #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_TIM11_HANDLER VectorA8 #define STM32_TIM11_NUMBER 26 @@ -381,13 +381,13 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */ #define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */ #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_TIM14_HANDLER VectorF4 #define STM32_TIM14_NUMBER 45