mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6749 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -163,7 +163,7 @@ extern "C" {
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void i2sStart(I2SDriver *i2sp, const I2SConfig *config);
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void i2sStop(I2SDriver *i2sp);
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void i2sStartExchange(I2SDriver *i2sp);
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void i2sStopTransfer(I2SDriver *i2sp);
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void i2sStopExchange(I2SDriver *i2sp);
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#ifdef __cplusplus
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}
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#endif
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@ -419,14 +419,22 @@ void i2s_lld_start_exchange(I2SDriver *i2sp) {
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*/
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void i2s_lld_stop_exchange(I2SDriver *i2sp) {
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/* Stop DMAs.*/
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if (NULL != i2sp->dmatx)
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/* Stop TX DMA, if enabled.*/
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if (NULL != i2sp->dmatx) {
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dmaStreamDisable(i2sp->dmatx);
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/* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
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to wait for TXE = 1 and BSY = 0.*/
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while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
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;
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}
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/* Stop SPI/I2S peripheral.*/
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i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
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/* Stop RX DMA, if enabled.*/
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if (NULL != i2sp->dmarx)
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dmaStreamDisable(i2sp->dmarx);
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/* Stop transfer.*/
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i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
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}
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#endif /* HAL_USE_I2S */
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@ -17,6 +17,28 @@
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#include "ch.h"
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#include "hal.h"
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#define I2S_BUF_SIZE 256
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static uint16_t i2s_rx_buf[I2S_BUF_SIZE];
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static void i2scallback(I2SDriver *i2sp, size_t offset, size_t n);
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static const I2SConfig i2scfg = {
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NULL,
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i2s_rx_buf,
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I2S_BUF_SIZE,
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i2scallback,
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0,
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16
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};
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static void i2scallback(I2SDriver *i2sp, size_t offset, size_t n) {
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(void)i2sp;
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(void)offset;
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(void)n;
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}
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/*
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* Application entry point.
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*/
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@ -33,9 +55,22 @@ int main(void) {
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chSysInit();
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/*
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* Normal main() thread activity, in this demo it does nothing.
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* Starting and configuring the I2S driver 2.
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*/
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i2sStart(&I2SD2, &i2scfg);
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/*
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* Starting continuous I2S transfer.
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*/
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i2sStartExchange(&I2SD2);
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/*
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* Normal main() thread activity, if the button is pressed then the I2s
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* transfer is stopped.
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*/
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while (TRUE) {
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if (palReadPad(GPIOA, GPIOA_BUTTON))
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i2sStopExchange(&I2SD2);
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chThdSleepMilliseconds(500);
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}
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return 0;
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@ -54,7 +54,7 @@
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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#define STM32_PVD_ENABLE FALSE
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