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SPIv2 support added to L4 and L4+ families. Made GPIOv2 and GPIOv3 definitions more compatible (L4 affected). 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14955 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-10-26 10:42:40 +00:00
parent 205c3ab699
commit b73feac604
14 changed files with 141 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.h
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@ -61,10 +61,10 @@
#define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U) #define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U)
#define PAL_STM32_OSPEED_MASK (3U << 3U) #define PAL_STM32_OSPEED_MASK (3U << 3U)
#define PAL_STM32_OSPEED_LOW (0U << 3U) #define PAL_STM32_OSPEED_LOWEST (0U << 3U)
#define PAL_STM32_OSPEED_MEDIUM (1U << 3U) #define PAL_STM32_OSPEED_MID1 (1U << 3U)
#define PAL_STM32_OSPEED_FAST (2U << 3U) #define PAL_STM32_OSPEED_MID2 (2U << 3U)
#define PAL_STM32_OSPEED_HIGH (3U << 3U) #define PAL_STM32_OSPEED_HIGHEST (3U << 3U)
#define PAL_STM32_PUPDR_MASK (3U << 5U) #define PAL_STM32_PUPDR_MASK (3U << 5U)
#define PAL_STM32_PUPDR_FLOATING (0U << 5U) #define PAL_STM32_PUPDR_FLOATING (0U << 5U)

5
os/hal/ports/STM32/STM32L4xx+/hal_lld.h
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@ -44,6 +44,11 @@
/* Driver constants. */ /* Driver constants. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Requires use of SPIv2 driver model.
*/
#define HAL_LLD_SELECT_SPI_V2 TRUE
/** /**
* @name Platform identification * @name Platform identification
* @{ * @{

2
os/hal/ports/STM32/STM32L4xx+/platform.mk
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@ -39,7 +39,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver_v2.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk

2
os/hal/ports/STM32/STM32L4xx+/platform_l4p5_l4q5.mk
View File

@ -39,7 +39,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver_v2.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk

5
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -44,6 +44,11 @@
/* Driver constants. */ /* Driver constants. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Requires use of SPIv2 driver model.
*/
#define HAL_LLD_SELECT_SPI_V2 TRUE
/** /**
* @name Platform identification * @name Platform identification
* @{ * @{

2
os/hal/ports/STM32/STM32L4xx/platform.mk
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@ -40,7 +40,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver_v2.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk

2
os/hal/ports/STM32/STM32L4xx/platform_l412_l422.mk
View File

@ -36,7 +36,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver_v2.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk

2
os/hal/ports/STM32/STM32L4xx/platform_l432.mk
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@ -40,7 +40,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver_v2.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk

57
testhal/STM32/multi/SPI/cfg/stm32l476_discovery/portab.c
View File

@ -35,41 +35,48 @@
/*===========================================================================*/ /*===========================================================================*/
void spi_circular_cb(SPIDriver *spip); void spi_circular_cb(SPIDriver *spip);
void spi_error_cb(SPIDriver *spip);
/* /*
* Circular SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). * Circular SPI configuration (20MHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig c_spicfg = { const SPIConfig c_spicfg = {
true, .circular = true,
spi_circular_cb, .slave = false,
GPIOB, .data_cb = spi_circular_cb,
12, .error_cb = spi_error_cb,
0, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_0,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/* /*
* Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). * Maximum speed SPI configuration (20MHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig hs_spicfg = { const SPIConfig hs_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = spi_error_cb,
0, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_0,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/* /*
* Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). * Low speed SPI configuration (625kHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig ls_spicfg = { const SPIConfig ls_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = spi_error_cb,
SPI_CR1_BR_2 | SPI_CR1_BR_1, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_2 | SPI_CR1_BR_1,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/*===========================================================================*/ /*===========================================================================*/
@ -94,13 +101,13 @@ void portab_setup(void) {
* SPI2 I/O pins setup. * SPI2 I/O pins setup.
*/ */
palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New SCK. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 SCK. */
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New MISO. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 MISO. */
palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New MOSI. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 MOSI. */
palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGH); /* New CS. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 CS. */
palSetPad(GPIOB, 12); palSetPad(GPIOB, 12);
} }

2
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -312,7 +312,7 @@
*/ */
#define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE #define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY

81
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/portab.c
View File

@ -35,41 +35,60 @@
/*===========================================================================*/ /*===========================================================================*/
void spi_circular_cb(SPIDriver *spip); void spi_circular_cb(SPIDriver *spip);
void spi_error_cb(SPIDriver *spip);
/* /*
* Circular SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). * Circular SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig c_spicfg = { const SPIConfig c_spicfg = {
true, .circular = true,
spi_circular_cb, .slave = false,
GPIOB, .data_cb = spi_circular_cb,
12, .error_cb = spi_error_cb,
0, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_0,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/* /*
* Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). * Maximum speed SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig hs_spicfg = { const SPIConfig hs_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = spi_error_cb,
0, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_0,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/* /*
* Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). * Low speed SPI configuration (937.5kHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig ls_spicfg = { const SPIConfig ls_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = spi_error_cb,
SPI_CR1_BR_2 | SPI_CR1_BR_1, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_2 | SPI_CR1_BR_1,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
};
/*
* Slave SPI configuration (CPHA=0, CPOL=0, MSb first).
*/
const SPIConfig sl_spicfg = {
.circular = false,
.slave = true,
.data_cb = NULL,
.error_cb = spi_error_cb,
.cr1 = 0U,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/*===========================================================================*/ /*===========================================================================*/
@ -94,14 +113,26 @@ void portab_setup(void) {
* SPI2 I/O pins setup. * SPI2 I/O pins setup.
*/ */
palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New SCK. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 SCK. */
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New MISO. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 MISO. */
palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New MOSI. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 MOSI. */
palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGH); /* New CS. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 CS. */
palSetPad(GPIOB, 12); palSetPad(GPIOB, 12);
/*
* SPI3 I/O pins setup.
*/
palSetPadMode(GPIOB, 3, PAL_MODE_ALTERNATE(6) |
PAL_STM32_OSPEED_HIGHEST); /* SPI3 SCK. */
palSetPadMode(GPIOB, 4, PAL_MODE_ALTERNATE(6) |
PAL_STM32_OSPEED_HIGHEST); /* SPI3 MISO. */
palSetPadMode(GPIOB, 5, PAL_MODE_ALTERNATE(6) |
PAL_STM32_OSPEED_HIGHEST); /* SPI3 MOSI. */
palSetPadMode(GPIOA, 4, PAL_MODE_ALTERNATE(6) |
PAL_STM32_OSPEED_HIGHEST); /* SPI3 NSSS. */
} }
/** @} */ /** @} */

2
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/portab.h
View File

@ -38,6 +38,7 @@
#define PORTAB_BUTTON_PRESSED PAL_HIGH #define PORTAB_BUTTON_PRESSED PAL_HIGH
#define PORTAB_SPI1 SPID2 #define PORTAB_SPI1 SPID2
#define PORTAB_SPI2 SPID3
/*===========================================================================*/ /*===========================================================================*/
/* Module pre-compile time settings. */ /* Module pre-compile time settings. */
@ -62,6 +63,7 @@
extern const SPIConfig c_spicfg; extern const SPIConfig c_spicfg;
extern const SPIConfig hs_spicfg; extern const SPIConfig hs_spicfg;
extern const SPIConfig ls_spicfg; extern const SPIConfig ls_spicfg;
extern const SPIConfig sl_spicfg;
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

53
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/portab.c
View File

@ -35,41 +35,48 @@
/*===========================================================================*/ /*===========================================================================*/
void spi_circular_cb(SPIDriver *spip); void spi_circular_cb(SPIDriver *spip);
void spi_error_cb(SPIDriver *spip);
/* /*
* Circular SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first). * Circular SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig c_spicfg = { const SPIConfig c_spicfg = {
true, .circular = true,
spi_circular_cb, .slave = false,
GPIOB, .data_cb = spi_circular_cb,
12, .error_cb = spi_error_cb,
0, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_0,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/* /*
* Maximum speed SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first). * Maximum speed SPI configuration (30MHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig hs_spicfg = { const SPIConfig hs_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = spi_error_cb,
0, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_0,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/* /*
* Low speed SPI configuration (468.75kHz, CPHA=0, CPOL=0, MSb first). * Low speed SPI configuration (937.5kHz, CPHA=0, CPOL=0, MSb first).
*/ */
const SPIConfig ls_spicfg = { const SPIConfig ls_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = spi_error_cb,
SPI_CR1_BR_2 | SPI_CR1_BR_1, .ssport = GPIOB,
0 .sspad = 12U,
.cr1 = SPI_CR1_BR_2 | SPI_CR1_BR_1,
.cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
}; };
/*===========================================================================*/ /*===========================================================================*/
@ -94,13 +101,13 @@ void portab_setup(void) {
* SPI2 I/O pins setup. * SPI2 I/O pins setup.
*/ */
palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New SCK. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 SCK. */
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New MISO. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 MISO. */
palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) |
PAL_STM32_OSPEED_HIGH); /* New MOSI. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 MOSI. */
palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGH); /* New CS. */ PAL_STM32_OSPEED_HIGHEST); /* SPI2 CS. */
palSetPad(GPIOB, 12); palSetPad(GPIOB, 12);
} }

2
testhal/STM32/multi/SPI/main.c
View File

@ -167,7 +167,7 @@ int main(void) {
txbuf[i] = (uint8_t)i; txbuf[i] = (uint8_t)i;
cacheBufferFlush(&txbuf[0], sizeof txbuf); cacheBufferFlush(&txbuf[0], sizeof txbuf);
#if SPI_SUPPORTS_SLAVE_MODE == TRUE #if (SPI_SUPPORTS_SLAVE_MODE == TRUE) && defined(PORTAB_SPI2)
spiStart(&PORTAB_SPI1, &hs_spicfg); /* Master transfer parameters. */ spiStart(&PORTAB_SPI1, &hs_spicfg); /* Master transfer parameters. */
spiStart(&PORTAB_SPI2, &sl_spicfg); /* Slave transfer parameters. */ spiStart(&PORTAB_SPI2, &sl_spicfg); /* Slave transfer parameters. */
do { do {