From b9f314c50bd1130725b1309fc69205b915b7cc5b Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 19 May 2021 07:00:59 +0000 Subject: [PATCH] Enforced PWR_CR1_DBP for default configuration. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14392 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/STM32G4xx/hal_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_lld.c index 5f1080cdf..3b1364b0c 100644 --- a/os/hal/ports/STM32/STM32G4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32G4xx/hal_lld.c @@ -65,7 +65,7 @@ const halclkcfg_t hal_clkcfg_reset = { * @brief Default clock configuration. */ const halclkcfg_t hal_clkcfg_default = { - .pwr_cr1 = STM32_VOS_RANGE1, + .pwr_cr1 = STM32_VOS_RANGE1 | PWR_CR1_DBP, .pwr_cr2 = STM32_PWR_CR2, .pwr_cr3 = STM32_PWR_CR3, .pwr_cr4 = STM32_PWR_CR4,