Fixed a problem in L4+ PLLSAIx initialization, added options to mcuconf.h, updated mcuconf generator tool.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12397 110e8d01-0319-4d1e-a829-52ad28d1bb01

demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h

@@ -69,11 +69,13 @@
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE                1
 #define STM32_PLLSAI1N_VALUE                72
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
+#define STM32_PLLSAI2M_VALUE                1
 #define STM32_PLLSAI2N_VALUE                72
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
@@ -321,5 +323,18 @@
 /*
  * WSPI driver system settings.
  */
+#define STM32_WSPI_USE_OCTOSPI1             TRUE
+#define STM32_WSPI_USE_OCTOSPI2             TRUE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip)    osalSysHalt("DMA failure")
 
 #endif /* MCUCONF_H */

demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h

@@ -69,11 +69,13 @@
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE                4
 #define STM32_PLLSAI1N_VALUE                72
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
+#define STM32_PLLSAI2M_VALUE                4
 #define STM32_PLLSAI2N_VALUE                72
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
@@ -321,5 +323,18 @@
 /*
  * WSPI driver system settings.
  */
+#define STM32_WSPI_USE_OCTOSPI1             TRUE
+#define STM32_WSPI_USE_OCTOSPI2             TRUE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip)    osalSysHalt("DMA failure")
 
 #endif /* MCUCONF_H */

os/hal/boards/ST_STM32L4R9I_DISCOVERY/board.h

@@ -27,7 +27,7 @@
 /*===========================================================================*/
 
 /*
- * Setup for STMicroelectronics STM32L4R9I Discovery board.
+ * Setup for STMicroelectronics STM32L4R9I-Discovery board.
  */
 
 /*
@@ -183,10 +183,10 @@
 #define GPIOG_PIN14                 14U
 #define GPIOG_OCTOSPIM_P2_DQS       15U
 
-#define GPIOH_PIN0                  0U
+#define GPIOH_OSC_IN                0U
-#define GPIOH_PIN1                  1U
+#define GPIOH_OSC_OUT               1U
 #define GPIOH_PIN2                  2U
-#define GPIOH_PIN3                  3U
+#define GPIOH_BOOT0                 3U
 #define GPIOH_LED                   4U
 #define GPIOH_LED_GREEN             4U
 #define GPIOH_PIN5                  5U
@@ -242,6 +242,9 @@
 #define LINE_OCTOSPIM_P2_IO7        PAL_LINE(GPIOG, 10U)
 #define LINE_OCTOSPIM_P2_NCS        PAL_LINE(GPIOG, 12U)
 #define LINE_OCTOSPIM_P2_DQS        PAL_LINE(GPIOG, 15U)
+#define LINE_OSC_IN                 PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT                PAL_LINE(GPIOH, 1U)
+#define LINE_BOOT0                  PAL_LINE(GPIOH, 3U)
 #define LINE_LED                    PAL_LINE(GPIOH, 4U)
 #define LINE_LED_GREEN              PAL_LINE(GPIOH, 4U)
 #define LINE_OCTOSPIM_P2_IO3        PAL_LINE(GPIOH, 8U)
@@ -1340,10 +1343,10 @@
 /*
  * GPIOH setup:
  *
- * PH0  - PIN0                      (analog).
+ * PH0  - OSC_IN                    (analog).
- * PH1  - PIN1                      (analog).
+ * PH1  - OSC_OUT                   (analog).
  * PH2  - PIN2                      (analog).
- * PH3  - PIN3                      (input floating).
+ * PH3  - BOOT0                     (input floating).
  * PH4  - LED LED_GREEN             (output pushpull minimum).
  * PH5  - PIN5                      (analog).
  * PH6  - PIN6                      (analog).
@@ -1357,10 +1360,10 @@
  * PH14 - PIN14                     (analog).
  * PH15 - PIN15                     (analog).
  */
-#define VAL_GPIOH_MODER             (PIN_MODE_ANALOG(GPIOH_PIN0) |          \
+#define VAL_GPIOH_MODER             (PIN_MODE_ANALOG(GPIOH_OSC_IN) |        \
-                                     PIN_MODE_ANALOG(GPIOH_PIN1) |          \
+                                     PIN_MODE_ANALOG(GPIOH_OSC_OUT) |       \
                                      PIN_MODE_ANALOG(GPIOH_PIN2) |          \
-                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_BOOT0) |          \
                                      PIN_MODE_OUTPUT(GPIOH_LED) |           \
                                      PIN_MODE_ANALOG(GPIOH_PIN5) |          \
                                      PIN_MODE_ANALOG(GPIOH_PIN6) |          \
@@ -1373,10 +1376,10 @@
                                      PIN_MODE_ANALOG(GPIOH_PIN13) |         \
                                      PIN_MODE_ANALOG(GPIOH_PIN14) |         \
                                      PIN_MODE_ANALOG(GPIOH_PIN15))
-#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) |       \
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
-                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
                                      PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
-                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_BOOT0) |      \
                                      PIN_OTYPE_PUSHPULL(GPIOH_LED) |        \
                                      PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
                                      PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
@@ -1389,10 +1392,10 @@
                                      PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
                                      PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
                                      PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
-#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOH_PIN0) |       \
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOH_OSC_IN) |     \
-                                     PIN_OSPEED_VERYLOW(GPIOH_PIN1) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOH_OSC_OUT) |    \
                                      PIN_OSPEED_VERYLOW(GPIOH_PIN2) |       \
-                                     PIN_OSPEED_VERYLOW(GPIOH_PIN3) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOH_BOOT0) |      \
                                      PIN_OSPEED_VERYLOW(GPIOH_LED) |        \
                                      PIN_OSPEED_VERYLOW(GPIOH_PIN5) |       \
                                      PIN_OSPEED_VERYLOW(GPIOH_PIN6) |       \
@@ -1405,10 +1408,10 @@
                                      PIN_OSPEED_VERYLOW(GPIOH_PIN13) |      \
                                      PIN_OSPEED_VERYLOW(GPIOH_PIN14) |      \
                                      PIN_OSPEED_VERYLOW(GPIOH_PIN15))
-#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_PIN0) |       \
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
-                                     PIN_PUPDR_FLOATING(GPIOH_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
                                      PIN_PUPDR_FLOATING(GPIOH_PIN2) |       \
-                                     PIN_PUPDR_FLOATING(GPIOH_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_BOOT0) |      \
                                      PIN_PUPDR_FLOATING(GPIOH_LED) |        \
                                      PIN_PUPDR_FLOATING(GPIOH_PIN5) |       \
                                      PIN_PUPDR_FLOATING(GPIOH_PIN6) |       \
@@ -1421,10 +1424,10 @@
                                      PIN_PUPDR_FLOATING(GPIOH_PIN13) |      \
                                      PIN_PUPDR_FLOATING(GPIOH_PIN14) |      \
                                      PIN_PUPDR_FLOATING(GPIOH_PIN15))
-#define VAL_GPIOH_ODR               (PIN_ODR_LOW(GPIOH_PIN0) |              \
+#define VAL_GPIOH_ODR               (PIN_ODR_LOW(GPIOH_OSC_IN) |            \
-                                     PIN_ODR_LOW(GPIOH_PIN1) |              \
+                                     PIN_ODR_LOW(GPIOH_OSC_OUT) |           \
                                      PIN_ODR_LOW(GPIOH_PIN2) |              \
-                                     PIN_ODR_LOW(GPIOH_PIN3) |              \
+                                     PIN_ODR_LOW(GPIOH_BOOT0) |             \
                                      PIN_ODR_LOW(GPIOH_LED) |               \
                                      PIN_ODR_LOW(GPIOH_PIN5) |              \
                                      PIN_ODR_LOW(GPIOH_PIN6) |              \
@@ -1437,10 +1440,10 @@
                                      PIN_ODR_LOW(GPIOH_PIN13) |             \
                                      PIN_ODR_LOW(GPIOH_PIN14) |             \
                                      PIN_ODR_LOW(GPIOH_PIN15))
-#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_PIN0, 0U) |          \
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) |        \
-                                     PIN_AFIO_AF(GPIOH_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) |       \
                                      PIN_AFIO_AF(GPIOH_PIN2, 0U) |          \
-                                     PIN_AFIO_AF(GPIOH_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_BOOT0, 0U) |         \
                                      PIN_AFIO_AF(GPIOH_LED, 0U) |           \
                                      PIN_AFIO_AF(GPIOH_PIN5, 0U) |          \
                                      PIN_AFIO_AF(GPIOH_PIN6, 0U) |          \
@@ -1453,10 +1456,10 @@
                                      PIN_AFIO_AF(GPIOH_PIN13, 0U) |         \
                                      PIN_AFIO_AF(GPIOH_PIN14, 0U) |         \
                                      PIN_AFIO_AF(GPIOH_PIN15, 0U))
-#define VAL_GPIOH_ASCR              (PIN_ASCR_DISABLED(GPIOH_PIN0) |        \
+#define VAL_GPIOH_ASCR              (PIN_ASCR_DISABLED(GPIOH_OSC_IN) |      \
-                                     PIN_ASCR_DISABLED(GPIOH_PIN1) |        \
+                                     PIN_ASCR_DISABLED(GPIOH_OSC_OUT) |     \
                                      PIN_ASCR_DISABLED(GPIOH_PIN2) |        \
-                                     PIN_ASCR_DISABLED(GPIOH_PIN3) |        \
+                                     PIN_ASCR_DISABLED(GPIOH_BOOT0) |       \
                                      PIN_ASCR_DISABLED(GPIOH_LED) |         \
                                      PIN_ASCR_DISABLED(GPIOH_PIN5) |        \
                                      PIN_ASCR_DISABLED(GPIOH_PIN6) |        \
@@ -1469,10 +1472,10 @@
                                      PIN_ASCR_DISABLED(GPIOH_PIN13) |       \
                                      PIN_ASCR_DISABLED(GPIOH_PIN14) |       \
                                      PIN_ASCR_DISABLED(GPIOH_PIN15))
-#define VAL_GPIOH_LOCKR             (PIN_LOCKR_DISABLED(GPIOH_PIN0) |       \
+#define VAL_GPIOH_LOCKR             (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) |     \
-                                     PIN_LOCKR_DISABLED(GPIOH_PIN1) |       \
+                                     PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) |    \
                                      PIN_LOCKR_DISABLED(GPIOH_PIN2) |       \
-                                     PIN_LOCKR_DISABLED(GPIOH_PIN3) |       \
+                                     PIN_LOCKR_DISABLED(GPIOH_BOOT0) |      \
                                      PIN_LOCKR_DISABLED(GPIOH_LED) |        \
                                      PIN_LOCKR_DISABLED(GPIOH_PIN5) |       \
                                      PIN_LOCKR_DISABLED(GPIOH_PIN6) |       \

os/hal/boards/ST_STM32L4R9I_DISCOVERY/cfg/board.chcfg

@@ -1162,7 +1162,7 @@
 				AnalogSwitch="Disabled"
 				PinLock="Disabled"
 				Alternate="0"
-				ID=""
+				ID="OSC_IN"
 				Resistor="Floating"
 				Mode="Analog"
 				Level="Low" />
@@ -1172,7 +1172,7 @@
 				AnalogSwitch="Disabled"
 				PinLock="Disabled"
 				Alternate="0"
-				ID=""
+				ID="OSC_OUT"
 				Resistor="Floating"
 				Mode="Analog"
 				Level="Low" />
@@ -1192,10 +1192,10 @@
 				AnalogSwitch="Disabled"
 				PinLock="Disabled"
 				Alternate="0"
-				ID=""
+				ID="BOOT0"
 				Resistor="Floating"
 				Mode="Input"
-				Level="Low" />
+				Level="Low" ></pin3>
 			<pin4
 				Type="PushPull"
 				Speed="Minimum"

os/hal/ports/STM32/STM32L4xx+/hal_lld.c

@@ -268,19 +268,11 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
   /* PLLM and PLLSRC are common to all PLLs.*/
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
   RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR  |
                  STM32_PLLREN  | STM32_PLLQ  |
                  STM32_PLLQEN  | STM32_PLLP  |
                  STM32_PLLPEN  | STM32_PLLN  |
                  STM32_PLLM    | STM32_PLLSRC;
-#else
-  RCC->PLLCFGR = STM32_PLLR   | STM32_PLLREN |
-                 STM32_PLLQ   | STM32_PLLQEN |
-                 STM32_PLLP   | STM32_PLLPEN |
-                 STM32_PLLN   | STM32_PLLM   |
-                 STM32_PLLSRC;
-#endif
 #endif
 
 #if STM32_ACTIVATE_PLL
@@ -294,17 +286,11 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLLSAI1
   /* PLLSAI1 activation.*/
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
   RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
                      STM32_PLLSAI1REN  | STM32_PLLSAI1Q |
                      STM32_PLLSAI1QEN  | STM32_PLLSAI1P |
-                     STM32_PLLSAI1PEN  | STM32_PLLSAI1N;
+                     STM32_PLLSAI1PEN  | STM32_PLLSAI1N |
-#else
+                     STM32_PLLSAI1M;
-  RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
-                     STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
-                     STM32_PLLSAI1P | STM32_PLLSAI1PEN |
-                     STM32_PLLSAI1N;
-#endif
   RCC->CR |= RCC_CR_PLLSAI1ON;
 
   /* Waiting for PLL lock.*/
@@ -314,15 +300,10 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLLSAI2
   /* PLLSAI2 activation.*/
-#if defined(STM32L496xx) || defined(STM32L4A6xx)
   RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
                      STM32_PLLSAI2REN  | STM32_PLLSAI2P |
-                     STM32_PLLSAI2PEN  | STM32_PLLSAI2N;
+                     STM32_PLLSAI2PEN  | STM32_PLLSAI2N |
-#else
+                     STM32_PLLSAI2M;
-  RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
-                     STM32_PLLSAI2P | STM32_PLLSAI2PEN |
-                     STM32_PLLSAI2N;
-#endif
   RCC->CR |= RCC_CR_PLLSAI2ON;
 
   /* Waiting for PLL lock.*/

os/hal/ports/STM32/STM32L4xx+/hal_lld.h

@@ -468,7 +468,7 @@
 
 /**
  * @brief   PLLM divider value.
- * @note    The allowed values are 1..8.
+ * @note    The allowed values are 1..16.
  * @note    The default value is calculated for a 120MHz system clock from
  *          the internal 4MHz MSI clock.
  */
@@ -571,6 +571,16 @@
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
 #endif
 
+/**
+ * @brief   PLLSAI1M divider value.
+ * @note    The allowed values are 1..16.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLSAI1M_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1M_VALUE                1
+#endif
+
 /**
  * @brief   PLLSAI1N multiplier value.
  * @note    The allowed values are 8..127.
@@ -611,6 +621,16 @@
 #define STM32_PLLSAI1R_VALUE                6
 #endif
 
+/**
+ * @brief   PLLSAI2M divider value.
+ * @note    The allowed values are 1..16.
+ * @note    The default value is calculated for a 120MHz system clock from
+ *          the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLSAI2M_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2M_VALUE                1
+#endif
+
 /**
  * @brief   PLLSAI2N multiplier value.
  * @note    The allowed values are 8..127.
@@ -1232,7 +1252,7 @@
 /**
  * @brief   STM32_PLLM field.
  */
-#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) ||                 \
+#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) ||                 \
     defined(__DOXYGEN__)
 #define STM32_PLLM                  ((STM32_PLLM_VALUE - 1) << 4)
 #else
@@ -1240,7 +1260,7 @@
 #endif
 
 /**
- * @brief   PLLs input clock frequency.
+ * @brief   PLL input clock frequency.
  */
 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
 #define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)
@@ -1259,7 +1279,7 @@
 #endif
 
 /*
- * PLLs input frequency range check.
+ * PLL input frequency range check.
  */
 #if (STM32_PLLCLKIN != 0) &&                                                \
     ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
@@ -1573,6 +1593,44 @@
 #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
 #endif
 
+/**
+ * @brief   STM32_PLLSAI1M field.
+ */
+#if ((STM32_PLLSAI1M_VALUE >= 1) && (STM32_PLLSAI1M_VALUE <= 16)) ||        \
+    defined(__DOXYGEN__)
+#define STM32_PLLSAI1M              ((STM32_PLLSAI1M_VALUE - 1) << 4)
+#else
+#error "invalid STM32_PLLSAI1M_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLSAI1 input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1CLKIN          (STM32_HSECLK / STM32_PLLSAI1M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_MSI
+#define STM32_PLLSAI1CLKIN          (STM32_MSICLK / STM32_PLLSAI1M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLSAI1CLKIN          (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+#define STM32_PLLSAI1CLKIN          0
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLLSAI1 input frequency range check.
+ */
+#if (STM32_PLLSAI1CLKIN != 0) &&                                            \
+    ((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) ||                              \
+     (STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX))
+#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
 /*
  * PLLSAI1 enable check.
  */
@@ -1582,7 +1640,7 @@
     (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) ||                               \
     defined(__DOXYGEN__)
 
-#if STM32_PLLCLKIN == 0
+#if STM32_PLLSAI1CLKIN == 0
 #error "PLLSAI1 activation required but no PLL clock selected"
 #endif
 
@@ -1697,7 +1755,7 @@
 /**
  * @brief   PLLSAI1 VCO frequency.
  */
-#define STM32_PLLSAI1VCO             (STM32_PLLCLKIN * STM32_PLLSAI1N_VALUE)
+#define STM32_PLLSAI1VCO             (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE)
 
 /*
  * PLLSAI1 VCO frequency range check.
@@ -1750,6 +1808,44 @@
 #error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
 #endif
 
+/**
+ * @brief   STM32_PLLSAI2M field.
+ */
+#if ((STM32_PLLSAI2M_VALUE >= 1) && (STM32_PLLSAI2M_VALUE <= 16)) ||        \
+    defined(__DOXYGEN__)
+#define STM32_PLLSAI2M              ((STM32_PLLSAI2M_VALUE - 1) << 4)
+#else
+#error "invalid STM32_PLLSAI2M_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLSAI2 input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2CLKIN          (STM32_HSECLK / STM32_PLLSAI2M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_MSI
+#define STM32_PLLSAI2CLKIN          (STM32_MSICLK / STM32_PLLSAI2M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLSAI2CLKIN          (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+#define STM32_PLLSAI2CLKIN          0
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLLSAI2 input frequency range check.
+ */
+#if (STM32_PLLSAI2CLKIN != 0) &&                                            \
+    ((STM32_PLLSAI2CLKIN < STM32_PLLIN_MIN) ||                              \
+     (STM32_PLLSAI2CLKIN > STM32_PLLIN_MAX))
+#error "STM32_PLLSAI2CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
 /*
  * PLLSAI2 enable check.
  */
@@ -1758,7 +1854,7 @@
     (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) ||                               \
     defined(__DOXYGEN__)
 
-#if STM32_PLLCLKIN == 0
+#if STM32_PLLSAI2CLKIN == 0
 #error "PLLSAI2 activation required but no PLL clock selected"
 #endif
 
@@ -1843,7 +1939,7 @@
 /**
  * @brief   PLLSAI2 VCO frequency.
  */
-#define STM32_PLLSAI2VCO             (STM32_PLLCLKIN * STM32_PLLSAI2N_VALUE)
+#define STM32_PLLSAI2VCO             (STM32_PLLSAI2CLKIN * STM32_PLLSAI2N_VALUE)
 
 /*
  * PLLSAI2 VCO frequency range check.

testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h

@@ -69,11 +69,13 @@
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE                1
 #define STM32_PLLSAI1N_VALUE                72
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
+#define STM32_PLLSAI2M_VALUE                1
 #define STM32_PLLSAI2N_VALUE                72
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
@@ -321,5 +323,18 @@
 /*
  * WSPI driver system settings.
  */
+#define STM32_WSPI_USE_OCTOSPI1             TRUE
+#define STM32_WSPI_USE_OCTOSPI2             TRUE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip)    osalSysHalt("DMA failure")
 
 #endif /* MCUCONF_H */

testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h

@@ -69,11 +69,13 @@
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE                1
 #define STM32_PLLSAI1N_VALUE                72
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
+#define STM32_PLLSAI2M_VALUE                1
 #define STM32_PLLSAI2N_VALUE                72
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7
@@ -321,5 +323,18 @@
 /*
  * WSPI driver system settings.
  */
+#define STM32_WSPI_USE_OCTOSPI1             TRUE
+#define STM32_WSPI_USE_OCTOSPI2             TRUE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip)    osalSysHalt("DMA failure")
 
 #endif /* MCUCONF_H */

testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h

@@ -69,11 +69,13 @@
 #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE                1
 #define STM32_PLLSAI1N_VALUE                72
 #define STM32_PLLSAI1PDIV_VALUE             6
 #define STM32_PLLSAI1P_VALUE                7
 #define STM32_PLLSAI1Q_VALUE                6
 #define STM32_PLLSAI1R_VALUE                6
+#define STM32_PLLSAI2M_VALUE                1
 #define STM32_PLLSAI2N_VALUE                72
 #define STM32_PLLSAI2PDIV_VALUE             6
 #define STM32_PLLSAI2P_VALUE                7

tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl

@@ -80,11 +80,13 @@
 #define STM32_MCOSEL                        ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
 #define STM32_MCOPRE                        ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
 #define STM32_LSCOSEL                       ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
+#define STM32_PLLSAI1M_VALUE                ${doc.STM32_PLLSAI1M_VALUE!"1"}
 #define STM32_PLLSAI1N_VALUE                ${doc.STM32_PLLSAI1N_VALUE!"72"}
 #define STM32_PLLSAI1PDIV_VALUE             ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
 #define STM32_PLLSAI1P_VALUE                ${doc.STM32_PLLSAI1P_VALUE!"7"}
 #define STM32_PLLSAI1Q_VALUE                ${doc.STM32_PLLSAI1Q_VALUE!"6"}
 #define STM32_PLLSAI1R_VALUE                ${doc.STM32_PLLSAI1R_VALUE!"6"}
+#define STM32_PLLSAI2M_VALUE                ${doc.STM32_PLLSAI2M_VALUE!"1"}
 #define STM32_PLLSAI2N_VALUE                ${doc.STM32_PLLSAI2N_VALUE!"72"}
 #define STM32_PLLSAI2PDIV_VALUE             ${doc.STM32_PLLSAI2PDIV_VALUE!"6"}
 #define STM32_PLLSAI2P_VALUE                ${doc.STM32_PLLSAI2P_VALUE!"7"}
@@ -332,5 +334,18 @@
 /*
  * WSPI driver system settings.
  */
+#define STM32_WSPI_USE_OCTOSPI1             ${doc.STM32_WSPI_USE_OCTOSPI1!"TRUE"}
+#define STM32_WSPI_USE_OCTOSPI2             ${doc.STM32_WSPI_USE_OCTOSPI2!"TRUE"}
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI1_PRESCALER_VALUE!"1"}
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI2_PRESCALER_VALUE!"1"}
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    ${doc.STM32_WSPI_OCTOSPI1_IRQ_PRIORITY!"10"}
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    ${doc.STM32_WSPI_OCTOSPI2_IRQ_PRIORITY!"10"}
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     ${doc.STM32_WSPI_OCTOSPI1_DMA_CHANNEL!"9"}
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     ${doc.STM32_WSPI_OCTOSPI2_DMA_CHANNEL!"10"}
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    ${doc.STM32_WSPI_OCTOSPI1_DMA_PRIORITY!"1"}
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    ${doc.STM32_WSPI_OCTOSPI2_DMA_PRIORITY!"1"}
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY!"10"}
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY!"10"}
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip)    ${doc.STM32_WSPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
 
 #endif /* MCUCONF_H */