From c7ea01877fc8d940a863225dc419a15b387b4e1b Mon Sep 17 00:00:00 2001 From: vrepetenko Date: Wed, 28 Jul 2021 14:24:03 +0000 Subject: [PATCH] Fixed STM32_ADCSEL name, added STM32_RNGSEL default value. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14627 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h | 2 +- os/hal/ports/STM32/STM32WLxx/hal_lld.h | 11 +++++++++-- testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h | 2 +- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h index 249b8c295..9ad439cf3 100644 --- a/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h @@ -79,7 +79,7 @@ /* * Peripherals clock sources. */ -#define STM32_ADC1SEL STM32_ADCSEL_NOCLK +#define STM32_ADCSEL STM32_ADCSEL_NOCLK #define STM32_USART1SEL STM32_USART1SEL_SYSCLK #define STM32_USART2SEL STM32_USART2SEL_SYSCLK #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK diff --git a/os/hal/ports/STM32/STM32WLxx/hal_lld.h b/os/hal/ports/STM32/STM32WLxx/hal_lld.h index e387347a9..eb42e1fa6 100644 --- a/os/hal/ports/STM32/STM32WLxx/hal_lld.h +++ b/os/hal/ports/STM32/STM32WLxx/hal_lld.h @@ -708,6 +708,13 @@ #if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) #define STM32_RTCSEL STM32_RTCSEL_LSI #endif + +/** + * @brief RNG clock source. + */ +#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__) +#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK +#endif /** @} */ /*===========================================================================*/ @@ -1244,7 +1251,7 @@ * PLL enable check. */ #if (STM32_SW == STM32_SW_PLL) || \ - (STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ (STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \ (STM32_MCOSEL == STM32_MCOSEL_PLLQCLK) || \ @@ -1263,7 +1270,7 @@ /** * @brief STM32_PLLPEN field. */ -#if (STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \ +#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \ (STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \ defined(__DOXYGEN__) #define STM32_PLLPEN (1U << 16) diff --git a/testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h b/testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h index 582075512..24def5518 100644 --- a/testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h +++ b/testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h @@ -79,7 +79,7 @@ /* * Peripherals clock sources. */ -#define STM32_ADC1SEL STM32_ADCSEL_NOCLK +#define STM32_ADCSEL STM32_ADCSEL_NOCLK #define STM32_USART1SEL STM32_USART1SEL_SYSCLK #define STM32_USART2SEL STM32_USART2SEL_SYSCLK #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK