mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4337 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
906c6a6021
commit
c95c008bf0
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@ -0,0 +1,588 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/uart_lld.c
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* @brief STM32 low level UART driver code.
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*
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* @addtogroup UART
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_UART || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define USART1_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \
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STM32_USART1_RX_DMA_CHN)
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#define USART1_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \
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STM32_USART1_TX_DMA_CHN)
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#define USART2_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \
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STM32_USART2_RX_DMA_CHN)
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#define USART2_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \
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STM32_USART2_TX_DMA_CHN)
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#define USART3_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \
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STM32_USART3_RX_DMA_CHN)
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#define USART3_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
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STM32_USART3_TX_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief USART1 UART driver identifier.*/
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#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
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UARTDriver UARTD1;
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#endif
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/** @brief USART2 UART driver identifier.*/
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#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
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UARTDriver UARTD2;
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#endif
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/** @brief USART3 UART driver identifier.*/
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#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
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UARTDriver UARTD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Status bits translation.
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*
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* @param[in] sr USART SR register value
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*
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* @return The error flags.
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*/
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static uartflags_t translate_errors(uint16_t isr) {
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uartflags_t sts = 0;
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if (isr & USART_ISR_ORE)
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sts |= UART_OVERRUN_ERROR;
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if (isr & USART_ISR_PE)
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sts |= UART_PARITY_ERROR;
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if (isr & USART_ISR_FE)
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sts |= UART_FRAMING_ERROR;
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if (isr & USART_ISR_NE)
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sts |= UART_NOISE_ERROR;
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if (isr & USART_ISR_LBD)
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sts |= UART_BREAK_DETECTED;
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return sts;
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}
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/**
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* @brief Puts the receiver in the UART_RX_IDLE state.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void set_rx_idle_loop(UARTDriver *uartp) {
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uint32_t mode;
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/* RX DMA channel preparation, if the char callback is defined then the
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TCIE interrupt is enabled too.*/
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if (uartp->config->rxchar_cb == NULL)
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mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
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else
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mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
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dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
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dmaStreamSetTransactionSize(uartp->dmarx, 1);
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dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);
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dmaStreamEnable(uartp->dmarx);
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}
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/**
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* @brief USART de-initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void usart_stop(UARTDriver *uartp) {
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/* Stops RX and TX DMA channels.*/
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dmaStreamDisable(uartp->dmarx);
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dmaStreamDisable(uartp->dmatx);
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/* Stops USART operations.*/
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uartp->usart->CR1 = 0;
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uartp->usart->CR2 = 0;
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uartp->usart->CR3 = 0;
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}
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/**
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* @brief USART initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void usart_start(UARTDriver *uartp) {
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uint16_t cr1;
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USART_TypeDef *u = uartp->usart;
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/* Defensive programming, starting from a clean state.*/
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usart_stop(uartp);
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/* Baud rate setting.*/
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#if defined(STM32F0XX)
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if (uartp->usart == USART1)
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u->BRR = STM32_USART1CLK / uartp->config->speed;
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else
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u->BRR = STM32_PCLK / uartp->config->speed;
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#else /* !defined(STM32F0XX) */
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if (uartp->usart == USART1)
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u->BRR = STM32_PCLK2 / uartp->config->speed;
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else
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u->BRR = STM32_PCLK1 / uartp->config->speed;
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#endif /* !defined(STM32F0XX) */
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/* Resetting eventual pending status flags.*/
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u->ICR = 0xFFFFFFFF;
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/* Note that some bits are enforced because required for correct driver
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operations.*/
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if (uartp->config->txend2_cb == NULL)
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cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
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else
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cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
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USART_CR1_TCIE;
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u->CR1 = uartp->config->cr1 | cr1;
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u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
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u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
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USART_CR3_EIE;
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/* Starting the receiver idle loop.*/
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set_rx_idle_loop(uartp);
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}
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/**
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* @brief RX DMA common service routine.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_UART_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_UART_DMA_ERROR_HOOK(uartp);
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}
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#else
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(void)flags;
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#endif
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if (uartp->rxstate == UART_RX_IDLE) {
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/* Receiver in idle state, a callback is generated, if enabled, for each
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received character and then the driver stays in the same state.*/
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if (uartp->config->rxchar_cb != NULL)
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uartp->config->rxchar_cb(uartp, uartp->rxbuf);
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}
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else {
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/* Receiver in active state, a callback is generated, if enabled, after
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a completed transfer.*/
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dmaStreamDisable(uartp->dmarx);
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uartp->rxstate = UART_RX_COMPLETE;
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if (uartp->config->rxend_cb != NULL)
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uartp->config->rxend_cb(uartp);
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/* If the callback didn't explicitly change state then the receiver
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automatically returns to the idle state.*/
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if (uartp->rxstate == UART_RX_COMPLETE) {
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uartp->rxstate = UART_RX_IDLE;
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set_rx_idle_loop(uartp);
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}
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}
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}
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/**
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* @brief TX DMA common service routine.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_UART_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_UART_DMA_ERROR_HOOK(uartp);
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}
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#else
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(void)flags;
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#endif
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dmaStreamDisable(uartp->dmatx);
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/* A callback is generated, if enabled, after a completed transfer.*/
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uartp->txstate = UART_TX_COMPLETE;
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if (uartp->config->txend1_cb != NULL)
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uartp->config->txend1_cb(uartp);
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/* If the callback didn't explicitly change state then the transmitter
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automatically returns to the idle state.*/
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if (uartp->txstate == UART_TX_COMPLETE)
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uartp->txstate = UART_TX_IDLE;
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}
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/**
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* @brief USART common service routine.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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static void serve_usart_irq(UARTDriver *uartp) {
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uint16_t isr;
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USART_TypeDef *u = uartp->usart;
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/* Reading and clearing status.*/
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isr = u->ISR;
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u->ICR = isr;
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if (isr & (USART_ISR_LBD | USART_ISR_ORE | USART_ISR_NE |
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USART_ISR_FE | USART_ISR_PE)) {
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if (uartp->config->rxerr_cb != NULL)
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uartp->config->rxerr_cb(uartp, translate_errors(isr));
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}
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if (isr & USART_ISR_TC) {
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/* End of transmission, a callback is generated.*/
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if (uartp->config->txend2_cb != NULL)
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uartp->config->txend2_cb(uartp);
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
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/**
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* @brief USART1 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART1_IRQHandler) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD1);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_USART1 */
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#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
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/**
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* @brief USART2 IRQ handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(USART2_IRQHandler) {
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CH_IRQ_PROLOGUE();
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serve_usart_irq(&UARTD2);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_UART_USE_USART2 */
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|
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#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
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/**
|
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* @brief USART3 IRQ handler.
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*
|
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* @isr
|
||||
*/
|
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CH_IRQ_HANDLER(USART3_IRQHandler) {
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|
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CH_IRQ_PROLOGUE();
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|
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serve_usart_irq(&UARTD3);
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|
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CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_UART_USE_USART3 */
|
||||
|
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/*===========================================================================*/
|
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/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
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/**
|
||||
* @brief Low level UART driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void uart_lld_init(void) {
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|
||||
#if STM32_UART_USE_USART1
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uartObjectInit(&UARTD1);
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UARTD1.usart = USART1;
|
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UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);
|
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UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);
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#endif
|
||||
|
||||
#if STM32_UART_USE_USART2
|
||||
uartObjectInit(&UARTD2);
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UARTD2.usart = USART2;
|
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UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);
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UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);
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#endif
|
||||
|
||||
#if STM32_UART_USE_USART3
|
||||
uartObjectInit(&UARTD3);
|
||||
UARTD3.usart = USART3;
|
||||
UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);
|
||||
UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the UART peripheral.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void uart_lld_start(UARTDriver *uartp) {
|
||||
|
||||
uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
|
||||
if (uartp->state == UART_STOP) {
|
||||
#if STM32_UART_USE_USART1
|
||||
if (&UARTD1 == uartp) {
|
||||
bool_t b;
|
||||
b = dmaStreamAllocate(uartp->dmarx,
|
||||
STM32_UART_USART1_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
|
||||
b = dmaStreamAllocate(uartp->dmatx,
|
||||
STM32_UART_USART1_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
|
||||
rccEnableUSART1(FALSE);
|
||||
nvicEnableVector(USART1_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
|
||||
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
|
||||
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART2
|
||||
if (&UARTD2 == uartp) {
|
||||
bool_t b;
|
||||
b = dmaStreamAllocate(uartp->dmarx,
|
||||
STM32_UART_USART2_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
|
||||
b = dmaStreamAllocate(uartp->dmatx,
|
||||
STM32_UART_USART2_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
|
||||
rccEnableUSART2(FALSE);
|
||||
nvicEnableVector(USART2_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
|
||||
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
|
||||
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART3
|
||||
if (&UARTD3 == uartp) {
|
||||
bool_t b;
|
||||
b = dmaStreamAllocate(uartp->dmarx,
|
||||
STM32_UART_USART3_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
|
||||
b = dmaStreamAllocate(uartp->dmatx,
|
||||
STM32_UART_USART3_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
|
||||
(void *)uartp);
|
||||
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
|
||||
rccEnableUSART3(FALSE);
|
||||
nvicEnableVector(USART3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
|
||||
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
|
||||
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Static DMA setup, the transfer size depends on the USART settings,
|
||||
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
|
||||
if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
|
||||
uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
||||
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
|
||||
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
|
||||
uartp->rxbuf = 0;
|
||||
}
|
||||
|
||||
uartp->rxstate = UART_RX_IDLE;
|
||||
uartp->txstate = UART_TX_IDLE;
|
||||
usart_start(uartp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the UART peripheral.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void uart_lld_stop(UARTDriver *uartp) {
|
||||
|
||||
if (uartp->state == UART_READY) {
|
||||
usart_stop(uartp);
|
||||
dmaStreamRelease(uartp->dmarx);
|
||||
dmaStreamRelease(uartp->dmatx);
|
||||
|
||||
#if STM32_UART_USE_USART1
|
||||
if (&UARTD1 == uartp) {
|
||||
nvicDisableVector(USART1_IRQn);
|
||||
rccDisableUSART1(FALSE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART2
|
||||
if (&UARTD2 == uartp) {
|
||||
nvicDisableVector(USART2_IRQn);
|
||||
rccDisableUSART2(FALSE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART3
|
||||
if (&UARTD3 == uartp) {
|
||||
nvicDisableVector(USART3_IRQn);
|
||||
rccDisableUSART3(FALSE);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a transmission on the UART peripheral.
|
||||
* @note The buffers are organized as uint8_t arrays for data sizes below
|
||||
* or equal to 8 bits else it is organized as uint16_t arrays.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
* @param[in] n number of data frames to send
|
||||
* @param[in] txbuf the pointer to the transmit buffer
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
|
||||
|
||||
/* TX DMA channel preparation and start.*/
|
||||
dmaStreamSetMemory0(uartp->dmatx, txbuf);
|
||||
dmaStreamSetTransactionSize(uartp->dmatx, n);
|
||||
dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
|
||||
dmaStreamEnable(uartp->dmatx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops any ongoing transmission.
|
||||
* @note Stopping a transmission also suppresses the transmission callbacks.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
*
|
||||
* @return The number of data frames not transmitted by the
|
||||
* stopped transmit operation.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
size_t uart_lld_stop_send(UARTDriver *uartp) {
|
||||
|
||||
dmaStreamDisable(uartp->dmatx);
|
||||
return dmaStreamGetTransactionSize(uartp->dmatx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a receive operation on the UART peripheral.
|
||||
* @note The buffers are organized as uint8_t arrays for data sizes below
|
||||
* or equal to 8 bits else it is organized as uint16_t arrays.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
* @param[in] n number of data frames to send
|
||||
* @param[out] rxbuf the pointer to the receive buffer
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
|
||||
|
||||
/* Stopping previous activity (idle state).*/
|
||||
dmaStreamDisable(uartp->dmarx);
|
||||
|
||||
/* RX DMA channel preparation and start.*/
|
||||
dmaStreamSetMemory0(uartp->dmarx, rxbuf);
|
||||
dmaStreamSetTransactionSize(uartp->dmarx, n);
|
||||
dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
|
||||
dmaStreamEnable(uartp->dmarx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops any ongoing receive operation.
|
||||
* @note Stopping a receive operation also suppresses the receive callbacks.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
*
|
||||
* @return The number of data frames not received by the
|
||||
* stopped receive operation.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
size_t uart_lld_stop_receive(UARTDriver *uartp) {
|
||||
size_t n;
|
||||
|
||||
dmaStreamDisable(uartp->dmarx);
|
||||
n = dmaStreamGetTransactionSize(uartp->dmarx);
|
||||
set_rx_idle_loop(uartp);
|
||||
return n;
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_UART */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32/uart_lld.h
|
||||
* @brief STM32 low level UART driver header.
|
||||
*
|
||||
* @addtogroup UART
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _UART_LLD_H_
|
||||
#define _UART_LLD_H_
|
||||
|
||||
#if HAL_USE_UART || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UART driver on USART1 enable switch.
|
||||
* @details If set to @p TRUE the support for USART1 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART driver on USART2 enable switch.
|
||||
* @details If set to @p TRUE the support for USART2 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief UART driver on USART3 enable switch.
|
||||
* @details If set to @p TRUE the support for USART3 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART1 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART2 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART3 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USART1 DMA error hook.
|
||||
* @note The default action for DMA errors is a system halt because DMA
|
||||
* error can only happen because programming errors.
|
||||
*/
|
||||
#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for USART1 RX operations.
|
||||
* @note This option is only available on platforms with enhanced DMA.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for USART1 TX operations.
|
||||
* @note This option is only available on platforms with enhanced DMA.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for USART2 RX operations.
|
||||
* @note This option is only available on platforms with enhanced DMA.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for USART2 TX operations.
|
||||
* @note This option is only available on platforms with enhanced DMA.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for USART3 RX operations.
|
||||
* @note This option is only available on platforms with enhanced DMA.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DMA stream used for USART3 TX operations.
|
||||
* @note This option is only available on platforms with enhanced DMA.
|
||||
*/
|
||||
#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
|
||||
#error "USART1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
|
||||
#error "USART2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
|
||||
#error "USART3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
|
||||
!STM32_UART_USE_USART3
|
||||
#error "UART driver activated but no USART/UART peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
|
||||
STM32_USART1_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to USART1 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \
|
||||
STM32_USART1_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to USART1 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \
|
||||
STM32_USART2_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to USART2 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \
|
||||
STM32_USART2_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to USART2 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART3 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \
|
||||
STM32_USART3_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to USART3 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART3 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \
|
||||
STM32_USART3_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to USART3 TX"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief UART driver condition flags type.
|
||||
*/
|
||||
typedef uint32_t uartflags_t;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an UART driver.
|
||||
*/
|
||||
typedef struct UARTDriver UARTDriver;
|
||||
|
||||
/**
|
||||
* @brief Generic UART notification callback type.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
*/
|
||||
typedef void (*uartcb_t)(UARTDriver *uartp);
|
||||
|
||||
/**
|
||||
* @brief Character received UART notification callback type.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
* @param[in] c received character
|
||||
*/
|
||||
typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
|
||||
|
||||
/**
|
||||
* @brief Receive error UART notification callback type.
|
||||
*
|
||||
* @param[in] uartp pointer to the @p UARTDriver object
|
||||
* @param[in] e receive error mask
|
||||
*/
|
||||
typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief End of transmission buffer callback.
|
||||
*/
|
||||
uartcb_t txend1_cb;
|
||||
/**
|
||||
* @brief Physical end of transmission callback.
|
||||
*/
|
||||
uartcb_t txend2_cb;
|
||||
/**
|
||||
* @brief Receive buffer filled callback.
|
||||
*/
|
||||
uartcb_t rxend_cb;
|
||||
/**
|
||||
* @brief Character received while out if the @p UART_RECEIVE state.
|
||||
*/
|
||||
uartccb_t rxchar_cb;
|
||||
/**
|
||||
* @brief Receive error callback.
|
||||
*/
|
||||
uartecb_t rxerr_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Bit rate.
|
||||
*/
|
||||
uint32_t speed;
|
||||
/**
|
||||
* @brief Initialization value for the CR1 register.
|
||||
*/
|
||||
uint16_t cr1;
|
||||
/**
|
||||
* @brief Initialization value for the CR2 register.
|
||||
*/
|
||||
uint16_t cr2;
|
||||
/**
|
||||
* @brief Initialization value for the CR3 register.
|
||||
*/
|
||||
uint16_t cr3;
|
||||
} UARTConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an UART driver.
|
||||
*/
|
||||
struct UARTDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
uartstate_t state;
|
||||
/**
|
||||
* @brief Transmitter state.
|
||||
*/
|
||||
uarttxstate_t txstate;
|
||||
/**
|
||||
* @brief Receiver state.
|
||||
*/
|
||||
uartrxstate_t rxstate;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const UARTConfig *config;
|
||||
#if defined(UART_DRIVER_EXT_FIELDS)
|
||||
UART_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the USART registers block.
|
||||
*/
|
||||
USART_TypeDef *usart;
|
||||
/**
|
||||
* @brief DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
/**
|
||||
* @brief Receive DMA channel.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmarx;
|
||||
/**
|
||||
* @brief Transmit DMA channel.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmatx;
|
||||
/**
|
||||
* @brief Default receive buffer while into @p UART_RX_IDLE state.
|
||||
*/
|
||||
volatile uint16_t rxbuf;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
|
||||
extern UARTDriver UARTD1;
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
|
||||
extern UARTDriver UARTD2;
|
||||
#endif
|
||||
|
||||
#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
|
||||
extern UARTDriver UARTD3;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void uart_lld_init(void);
|
||||
void uart_lld_start(UARTDriver *uartp);
|
||||
void uart_lld_stop(UARTDriver *uartp);
|
||||
void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
|
||||
size_t uart_lld_stop_send(UARTDriver *uartp);
|
||||
void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
|
||||
size_t uart_lld_stop_receive(UARTDriver *uartp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_UART */
|
||||
|
||||
#endif /* _UART_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -175,7 +175,7 @@
|
|||
support several new devices.
|
||||
- NEW: Demo for STM32F0-Discovery board.
|
||||
- NEW: Initial support for STM32F0xx devices, added a specific ADC driver.
|
||||
Validated EXT, GPT, ICU, PAL, PWM, Serial, SPI drivers.
|
||||
Validated EXT, GPT, ICU, PAL, PWM, Serial, SPI, UART drivers.
|
||||
- NEW: Added a common ancestor class to the SDC and MMC_SPI drivers. This
|
||||
allows to share code and definitions.
|
||||
- NEW: Modified the SDC driver to implement the new block devices abstract
|
||||
|
|
|
|||
Loading…
Reference in New Issue