diff --git a/os/hal/ports/common/ARMCMx/nvic.c b/os/hal/ports/common/ARMCMx/nvic.c
index d99237f69..1c7179ac4 100644
--- a/os/hal/ports/common/ARMCMx/nvic.c
+++ b/os/hal/ports/common/ARMCMx/nvic.c
@@ -126,7 +126,8 @@ void nvicDisableVector(uint32_t n) {
 
   NVIC->__ICER[n >> 5U] = 1U << (n & 0x1FU);
   NVIC->__ICPR[n >> 5U] = 1U << (n & 0x1FU);
-#if defined(__CORE_CM0_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
+#if defined(__CORE_CM0_H_GENERIC) || defined(__CORE_CM0PLUS_H_GENERIC) ||   \
+    defined(__CORE_CM23_H_GENERIC)
   NVIC->__IPR[_IP_IDX(n)] = NVIC->__IPR[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n));
 #else
   NVIC->__IPR[n] = 0U;
@@ -147,7 +148,8 @@ void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
 
   osalDbgCheck(handler < 12U);
 
-#if defined(__CORE_CM0_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
+#if defined(__CORE_CM0_H_GENERIC) || defined(__CORE_CM0PLUS_H_GENERIC) ||   \
+    defined(__CORE_CM23_H_GENERIC)
   SCB->__SHPR[_SHP_IDX(handler)] = (SCB->__SHPR[_SHP_IDX(handler)] & ~(0xFFU << _BIT_SHIFT(handler))) |
                                    (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(handler));
 #else
diff --git a/readme.txt b/readme.txt
index 5a231fdff..f1c3a6661 100644
--- a/readme.txt
+++ b/readme.txt
@@ -84,6 +84,8 @@
 - NEW: EFL driver and demo for STM32F3xx.
 - NEW: New unit test subsystem under /os/test. Now it is officially
        ChibiOS/TEST.
+- FIX: Fixed function nvicSetSystemHandlerPriority() failing with CM0+ cores
+       (bug #1199)(backported to 20.3.4)(TBP to 21.6.1).
 - FIX: Fixed several problems in STM32L4xx PLL and GPIO settings (bug #1198)
        (backported to 20.3.4)(TBP to 21.6.1).
 - FIX: Fixed PLLSA1x input frequency calculated incorrectly (bug #1197)