mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5127 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
20d47035b0
commit
d078530805
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@ -0,0 +1,71 @@
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/*
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/* Initial setup of all defined pads, the list is terminated by a {0, 0, 0}.*/
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static const spc_siu_init_t spc_siu_init[] = {
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{PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
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{PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
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{PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
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{PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
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{PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
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{PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
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{PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
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{PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
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{PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
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{PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
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{0, 0, 0}
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};
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/* Initialization array for the PSMI registers.*/
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static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0
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};
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/**
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* @brief PAL setup.
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*/
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const PALConfig pal_default_config = {
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PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
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spc_siu_init,
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spc_padsels_init
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};
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#endif
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/*
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* Early initialization code.
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* This initialization must be performed just after stack setup and before
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* any other initialization.
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*/
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void __early_init(void) {
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spc_clock_init();
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/* SWT disabled.*/
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SWT.SR.R = 0xC520;
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SWT.SR.R = 0xD928;
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SWT.CR.R = 0xFF00000A;
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}
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/*
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* Board-specific initialization code.
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*/
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void boardInit(void) {
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}
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@ -0,0 +1,66 @@
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/*
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Setup for a generic SPC560Pxx proto board.
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*/
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/*
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* Board identifiers.
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*/
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#define BOARD_GENERIC_SPC56EL
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#define BOARD_NAME "Generic SPC56ELxx"
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/*
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* Board frequencies.
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*/
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#if !defined(SPC5_XOSC_CLK)
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#define SPC5_XOSC_CLK 40000000
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#endif
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/*
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* I/O definitions.
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*/
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#define PB_LIN0_TDX 2
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#define PB_LIN0_RDX 3
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#define PD_BUTTON1 0
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#define PD_BUTTON2 1
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#define PD_BUTTON3 2
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#define PD_BUTTON4 3
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#define PD_LED1 4
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#define PD_LED2 5
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#define PD_LED3 6
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#define PD_LED4 7
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/*
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* Support macros.
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*/
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#define PCR(port, pin) (((port) * 16) + (pin))
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#if !defined(_FROM_ASM_)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void boardInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FROM_ASM_ */
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#endif /* _BOARD_H_ */
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@ -0,0 +1,5 @@
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# List of all the board related files.
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BOARDSRC = ${CHIBIOS}/boards/GENERIC_SPC56EL/board.c
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# Required include directories
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BOARDINC = ${CHIBIOS}/boards/GENERIC_SPC56EL
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@ -46,9 +46,9 @@ PROJECT = ch
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# Imported source files
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# Imported source files
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CHIBIOS = ../..
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CHIBIOS = ../..
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#include $(CHIBIOS)/boards/GENERIC_SPC560EL/board.mk
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include $(CHIBIOS)/boards/GENERIC_SPC56EL/board.mk
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#include $(CHIBIOS)/os/hal/platforms/SPC560ELxx/platform.mk
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include $(CHIBIOS)/os/hal/platforms/SPC56ELxx/platform.mk
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#include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk
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include $(CHIBIOS)/os/ports/GCC/PPC/SPC56ELxx/port.mk
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include $(CHIBIOS)/os/kernel/kernel.mk
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include $(CHIBIOS)/os/kernel/kernel.mk
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#include $(CHIBIOS)/test/test.mk
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#include $(CHIBIOS)/test/test.mk
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@ -19,7 +19,7 @@
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*/
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*/
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#include "ch.h"
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#include "ch.h"
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//#include "hal.h"
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#include "hal.h"
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//#include "test.h"
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//#include "test.h"
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//#include "shell.h"
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//#include "shell.h"
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//#include "chprintf.h"
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//#include "chprintf.h"
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@ -175,7 +175,7 @@ int main(void) {
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* - Kernel initialization, the main() function becomes a thread and the
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* - Kernel initialization, the main() function becomes a thread and the
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* RTOS is active.
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* RTOS is active.
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*/
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*/
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// halInit();
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halInit();
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chSysInit();
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chSysInit();
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/*
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/*
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@ -53,7 +53,7 @@ CH_IRQ_HANDLER(vector59) {
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chSysUnlockFromIsr();
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chSysUnlockFromIsr();
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/* Resets the PIT channel 3 IRQ flag.*/
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/* Resets the PIT channel 3 IRQ flag.*/
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PIT.CH[0].TFLG.R = 1;
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PIT.CHANNEL[0].TFLG.R = 1;
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CH_IRQ_EPILOGUE();
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CH_IRQ_EPILOGUE();
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}
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}
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@ -90,10 +90,10 @@ void hal_lld_init(void) {
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SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
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SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
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reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
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reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
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PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
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PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
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PIT.CH[0].LDVAL.R = reg;
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PIT.CHANNEL[0].LDVAL.R = reg;
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PIT.CH[0].CVAL.R = reg;
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PIT.CHANNEL[0].CVAL.R = reg;
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PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
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PIT.CHANNEL[0].TFLG.R = 1; /* Interrupt flag cleared. */
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PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
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PIT.CHANNEL[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
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}
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}
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/**
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/**
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@ -107,7 +107,7 @@ void hal_lld_init(void) {
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void spc_clock_init(void) {
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void spc_clock_init(void) {
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/* Waiting for IRC stabilization before attempting anything else.*/
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/* Waiting for IRC stabilization before attempting anything else.*/
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while (!ME.GS.B.S_RC)
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while (!ME.GS.B.S_IRCOSC)
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;
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;
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#if !SPC5_NO_INIT
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#if !SPC5_NO_INIT
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/* Run modes initialization.*/
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/* Run modes initialization.*/
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ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
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ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
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ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
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// ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
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ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
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ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
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ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
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ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
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ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
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ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
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chSysHalt();
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chSysHalt();
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/* CFLASH settings calculated for a maximum clock of 64MHz.*/
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/* CFLASH settings calculated for a maximum clock of 64MHz.*/
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CFLASH.PFCR0.B.BK0_APC = 2;
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/* CFLASH.PFCR0.B.BK0_APC = 2;
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CFLASH.PFCR0.B.BK0_RWSC = 2;
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CFLASH.PFCR0.B.BK0_RWSC = 2;
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CFLASH.PFCR1.B.BK1_APC = 2;
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CFLASH.PFCR1.B.BK1_APC = 2;
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CFLASH.PFCR1.B.BK1_RWSC = 2;
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CFLASH.PFCR1.B.BK1_RWSC = 2;*/
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#endif /* !SPC5_NO_INIT */
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#endif /* !SPC5_NO_INIT */
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}
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}
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@ -196,7 +196,7 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
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;
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;
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/* Verifies that the mode has been effectively switched.*/
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/* Verifies that the mode has been effectively switched.*/
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if (ME.GS.B.S_CURRENTMODE != mode)
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if (ME.GS.B.S_CURRENT_MODE != mode)
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return CH_FAILED;
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return CH_FAILED;
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return CH_SUCCESS;
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return CH_SUCCESS;
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@ -69,7 +69,7 @@
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/**
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/**
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* @brief Maximum FMPLLs input clock frequency.
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* @brief Maximum FMPLLs input clock frequency.
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*/
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*/
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#define SPC5_FMPLLIN_MAX 16000000
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#define SPC5_FMPLLIN_MAX 40000000
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/**
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/**
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* @brief Maximum FMPLLs VCO clock frequency.
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* @brief Maximum FMPLLs VCO clock frequency.
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@ -84,7 +84,7 @@
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/**
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/**
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* @brief Maximum FMPLL0 output clock frequency.
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* @brief Maximum FMPLL0 output clock frequency.
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*/
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*/
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#define SPC5_FMPLL0_CLK_MAX 64000000
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#define SPC5_FMPLL0_CLK_MAX 120000000
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/**
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/**
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* @brief Maximum FMPLL1 output clock frequency.
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* @brief Maximum FMPLL1 output clock frequency.
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@ -104,6 +104,26 @@
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#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/
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#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/
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/** @} */
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/** @} */
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/**
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* @name MC_CGM_AC3_SC register bits definitions
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* @{
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|
*/
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#define SPC5_GCM_AC3_SC_SELCTL_MASK (15U << 24)
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#define SPC5_GCM_AC3_SC_SELCTL(n) ((n) << 24)
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#define SPC5_GCM_AC3_SC_SELCTL_IRC SPC5_GCM_AC3_SC_SELCTL(0)
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#define SPC5_GCM_AC3_SC_SELCTL_XOSC SPC5_GCM_AC3_SC_SELCTL(1)
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/** @} */
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|
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/**
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* @name MC_CGM_AC4_SC register bits definitions
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* @{
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||||||
|
*/
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#define SPC5_GCM_AC4_SC_SELCTL_MASK (15U << 24)
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|
#define SPC5_GCM_AC4_SC_SELCTL(n) ((n) << 24)
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|
#define SPC5_GCM_AC4_SC_SELCTL_IRC SPC5_GCM_AC4_SC_SELCTL(0)
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#define SPC5_GCM_AC4_SC_SELCTL_XOSC SPC5_GCM_AC4_SC_SELCTL(1)
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/** @} */
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|
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/**
|
/**
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* @name FMPLL_CR register bits definitions
|
* @name FMPLL_CR register bits definitions
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* @{
|
* @{
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@ -230,6 +250,13 @@
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#endif
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#endif
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|
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/**
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|
* @brief FMPLL0 Clock source.
|
||||||
|
*/
|
||||||
|
#if !defined(SPC5_FMPLL0_CLOCK_SOURCE) || defined(__DOXYGEN__)
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|
#define SPC5_FMPLL0_CLOCK_SOURCE SPC5_GCM_AC3_SC_SELCTL_XOSC
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|
#endif
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|
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/**
|
/**
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* @brief FMPLL0 IDF divider value.
|
* @brief FMPLL0 IDF divider value.
|
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
|
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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|
@ -254,6 +281,13 @@
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#endif
|
#endif
|
||||||
|
|
||||||
|
/**
|
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|
* @brief FMPLL1 Clock source.
|
||||||
|
*/
|
||||||
|
#if !defined(SPC5_FMPLL1_CLOCK_SOURCE) || defined(__DOXYGEN__)
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||||||
|
#define SPC5_FMPLL1_CLOCK_SOURCE SPC5_GCM_AC4_SC_SELCTL_XOSC
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||||||
|
#endif
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||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief FMPLL1 IDF divider value.
|
* @brief FMPLL1 IDF divider value.
|
||||||
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
|
* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
|
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|
@ -601,6 +635,15 @@
|
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#error "invalid SPC5_XOSC_CLK value specified"
|
#error "invalid SPC5_XOSC_CLK value specified"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/
|
||||||
|
#if SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_IRC
|
||||||
|
#define SPC5_FMPLL0_INPUT_CLK SPC5_IRC_CLK
|
||||||
|
#elif SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_XOSC
|
||||||
|
#define SPC5_FMPLL0_INPUT_CLK SPC5_XOSC_CLK
|
||||||
|
#else
|
||||||
|
#error "invalid SPC5_FMPLL0_CLOCK_SOURCE value specified"
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|
#endif
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|
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||||||
/* Check on SPC5_FMPLL0_IDF_VALUE.*/
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/* Check on SPC5_FMPLL0_IDF_VALUE.*/
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||||||
#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
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#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
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||||||
#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
|
#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
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||||||
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@ -628,7 +671,7 @@
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||||||
* @brief SPC5_FMPLL0_VCO_CLK clock point.
|
* @brief SPC5_FMPLL0_VCO_CLK clock point.
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||||||
*/
|
*/
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||||||
#define SPC5_FMPLL0_VCO_CLK \
|
#define SPC5_FMPLL0_VCO_CLK \
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||||||
((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
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((SPC5_FMPLL0_INPUT_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
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||||||
|
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||||||
/* Check on FMPLL0 VCO output.*/
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/* Check on FMPLL0 VCO output.*/
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||||||
#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
|
#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
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||||||
|
@ -647,6 +690,15 @@
|
||||||
#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
|
#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/
|
||||||
|
#if SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_IRC
|
||||||
|
#define SPC5_FMPLL1_INPUT_CLK SPC5_IRC_CLK
|
||||||
|
#elif SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_XOSC
|
||||||
|
#define SPC5_FMPLL1_INPUT_CLK SPC5_XOSC_CLK
|
||||||
|
#else
|
||||||
|
#error "invalid SPC5_FMPLL1_CLOCK_SOURCE value specified"
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Check on SPC5_FMPLL1_IDF_VALUE.*/
|
/* Check on SPC5_FMPLL1_IDF_VALUE.*/
|
||||||
#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
|
#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
|
||||||
#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
|
#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
|
||||||
|
@ -674,7 +726,7 @@
|
||||||
* @brief SPC5_FMPLL1_VCO_CLK clock point.
|
* @brief SPC5_FMPLL1_VCO_CLK clock point.
|
||||||
*/
|
*/
|
||||||
#define SPC5_FMPLL1_VCO_CLK \
|
#define SPC5_FMPLL1_VCO_CLK \
|
||||||
((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
|
((SPC5_FMPLL1_INPUT_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
|
||||||
|
|
||||||
/* Check on FMPLL1 VCO output.*/
|
/* Check on FMPLL1 VCO output.*/
|
||||||
#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
|
#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
|
||||||
|
|
|
@ -1,9 +1,9 @@
|
||||||
# List of all the SPC560Pxx platform files.
|
# List of all the SPC56ELxx platform files.
|
||||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \
|
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
|
${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
|
||||||
${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
|
${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
|
||||||
|
|
||||||
# Required include directories
|
# Required include directories
|
||||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \
|
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx \
|
||||||
${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
|
${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
|
||||||
${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
|
${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
|
||||||
|
|
|
@ -20,8 +20,8 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef _SPC560P_REGISTRY_H_
|
#ifndef _SPC56EL_REGISTRY_H_
|
||||||
#define _SPC560P_REGISTRY_H_
|
#define _SPC56EL_REGISTRY_H_
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Platform capabilities. */
|
/* Platform capabilities. */
|
||||||
|
@ -61,6 +61,6 @@
|
||||||
#define SPC5_SIUL_NUM_PADSELS 36
|
#define SPC5_SIUL_NUM_PADSELS 36
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
#endif /* _SPC560P_REGISTRY_H_ */
|
#endif /* _SPC56EL_REGISTRY_H_ */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
Loading…
Reference in New Issue