mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5397 35acf78f-673a-0410-8e92-d51de3d6d3f4
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acirillo87
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@ -33,17 +33,176 @@
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* @name STS register bits definitions
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* @{
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*/
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#define SPC5_STS_CMPF0 (1U << 0)
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#define SPC5_STS_CMPF1 (1U << 1)
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#define SPC5_STS_CMPF2 (1U << 2)
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#define SPC5_STS_CMPF3 (1U << 3)
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#define SPC5_STS_CMPF4 (1U << 4)
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#define SPC5_STS_CMPF5 (1U << 5)
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#define SPC5_STS_CFX0 (1U << 6)
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#define SPC5_STS_CFX1 (1U << 7)
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#define SPC5_STS_RF (1U << 12)
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#define SPC5_STS_REF (1U << 13)
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#define SPC5_STS_RUF (1U << 14)
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#define SPC5_FLEXPWM_STS_CMPF0 (1U << 0)
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#define SPC5_FLEXPWM_STS_CMPF1 (1U << 1)
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#define SPC5_FLEXPWM_STS_CMPF2 (1U << 2)
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#define SPC5_FLEXPWM_STS_CMPF3 (1U << 3)
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#define SPC5_FLEXPWM_STS_CMPF4 (1U << 4)
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#define SPC5_FLEXPWM_STS_CMPF5 (1U << 5)
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#define SPC5_FLEXPWM_STS_CFX0 (1U << 6)
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#define SPC5_FLEXPWM_STS_CFX1 (1U << 7)
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#define SPC5_FLEXPWM_STS_RF (1U << 12)
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#define SPC5_FLEXPWM_STS_REF (1U << 13)
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#define SPC5_FLEXPWM_STS_RUF (1U << 14)
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/** @} */
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/**
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* @name CTRL2 register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_CNTL2_CLKSEL0 (1U << 0)
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#define SPC5_FLEXPWM_CNTL2_CLKSEL1 (1U << 1)
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#define SPC5_FLEXPWM_CNTL2_RELOAD_SEL (1U << 2)
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#define SPC5_FLEXPWM_CNTL2_FORCE_SEL0 (1U << 3)
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#define SPC5_FLEXPWM_CNTL2_FORCE_SEL1 (1U << 4)
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#define SPC5_FLEXPWM_CNTL2_FORCE_SEL2 (1U << 5)
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#define SPC5_FLEXPWM_CNTL2_FORCE (1U << 6)
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#define SPC5_FLEXPWM_CNTL2_FRCEN (1U << 7)
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#define SPC5_FLEXPWM_CNTL2_INIT_SEL0 (1U << 8)
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#define SPC5_FLEXPWM_CNTL2_INIT_SEL1 (1U << 9)
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#define SPC5_FLEXPWM_CNTL2_PWM_X_INIT (1U << 10)
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#define SPC5_FLEXPWM_CNTL2_PWM_B_INIT (1U << 11)
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#define SPC5_FLEXPWM_CNTL2_PWM_A_INIT (1U << 12)
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#define SPC5_FLEXPWM_CNTL2_INDEP (1U << 13)
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#define SPC5_FLEXPWM_CNTL2_WAITEN (1U << 14)
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#define SPC5_FLEXPWM_CNTL2_DGBEN (1U << 15)
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/** @} */
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/**
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* @name CTRL1 register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_CNTL1_DBLEN (1U << 0)
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#define SPC5_FLEXPWM_CNTL1_PRSC0 (1U << 4)
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#define SPC5_FLEXPWM_CNTL1_PRSC1 (1U << 5)
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#define SPC5_FLEXPWM_CNTL1_PRSC2 (1U << 6)
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#define SPC5_FLEXPWM_CNTL1_FULL (1U << 10)
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#define SPC5_FLEXPWM_CNTL1_HALF (1U << 11)
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#define SPC5_FLEXPWM_CNTL1_LDFQ0 (1U << 12)
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#define SPC5_FLEXPWM_CNTL1_LDFQ1 (1U << 13)
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#define SPC5_FLEXPWM_CNTL1_LDFQ2 (1U << 14)
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#define SPC5_FLEXPWM_CNTL1_LDFQ3 (1U << 15)
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/** @} */
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/**
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* @name OCTRL register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_OCNTL_PWMXFS0 (1U << 0)
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#define SPC5_FLEXPWM_OCNTL_PWMXFS1 (1U << 1)
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#define SPC5_FLEXPWM_OCNTL_PWMBFS0 (1U << 2)
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#define SPC5_FLEXPWM_OCNTL_PWMBFS1 (1U << 3)
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#define SPC5_FLEXPWM_OCNTL_PWMAFS0 (1U << 4)
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#define SPC5_FLEXPWM_OCNTL_PWMAFS1 (1U << 5)
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#define SPC5_FLEXPWM_OCNTL_POLX (1U << 8)
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#define SPC5_FLEXPWM_OCNTL_POLB (1U << 9)
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#define SPC5_FLEXPWM_OCNTL_POLA (1U << 10)
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#define SPC5_FLEXPWM_OCNTL_PWMX_IN (1U << 13)
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#define SPC5_FLEXPWM_OCNTL_PWMB_IN (1U << 14)
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#define SPC5_FLEXPWM_OCNTL_PWMA_IN (1U << 15)
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/** @} */
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/**
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* @name INTEN register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_INTEN_CMPIE0 (1U << 0)
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#define SPC5_FLEXPWM_INTEN_CMPIE1 (1U << 1)
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#define SPC5_FLEXPWM_INTEN_CMPIE2 (1U << 2)
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#define SPC5_FLEXPWM_INTEN_CMPIE3 (1U << 3)
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#define SPC5_FLEXPWM_INTEN_CMPIE4 (1U << 4)
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#define SPC5_FLEXPWM_INTEN_CMPIE5 (1U << 5)
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#define SPC5_FLEXPWM_INTEN_CX0IE (1U << 6)
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#define SPC5_FLEXPWM_INTEN_CX1IE (1U << 7)
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#define SPC5_FLEXPWM_INTEN_RIE (1U << 12)
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#define SPC5_FLEXPWM_INTEN_REIE (1U << 13)
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/** @} */
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/**
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* @name OUTEN register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_OUTEN_PWMX_EN0 (1U << 0)
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#define SPC5_FLEXPWM_OUTEN_PWMX_EN1 (1U << 1)
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#define SPC5_FLEXPWM_OUTEN_PWMX_EN2 (1U << 2)
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#define SPC5_FLEXPWM_OUTEN_PWMX_EN3 (1U << 3)
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#define SPC5_FLEXPWM_OUTEN_PWMB_EN0 (1U << 4)
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#define SPC5_FLEXPWM_OUTEN_PWMB_EN1 (1U << 5)
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#define SPC5_FLEXPWM_OUTEN_PWMB_EN2 (1U << 6)
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#define SPC5_FLEXPWM_OUTEN_PWMB_EN3 (1U << 7)
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#define SPC5_FLEXPWM_OUTEN_PWMA_EN0 (1U << 8)
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#define SPC5_FLEXPWM_OUTEN_PWMA_EN1 (1U << 9)
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#define SPC5_FLEXPWM_OUTEN_PWMA_EN2 (1U << 10)
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#define SPC5_FLEXPWM_OUTEN_PWMA_EN3 (1U << 11)
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/** @} */
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/**
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* @name MASK register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_MASK_MASKX0 (1U << 0)
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#define SPC5_FLEXPWM_MASK_MASKX1 (1U << 1)
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#define SPC5_FLEXPWM_MASK_MASKX2 (1U << 2)
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#define SPC5_FLEXPWM_MASK_MASKX3 (1U << 3)
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#define SPC5_FLEXPWM_MASK_MASKB0 (1U << 4)
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#define SPC5_FLEXPWM_MASK_MASKB1 (1U << 5)
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#define SPC5_FLEXPWM_MASK_MASKB2 (1U << 6)
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#define SPC5_FLEXPWM_MASK_MASKB3 (1U << 7)
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#define SPC5_FLEXPWM_MASK_MASKA0 (1U << 8)
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#define SPC5_FLEXPWM_MASK_MASKA1 (1U << 9)
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#define SPC5_FLEXPWM_MASK_MASKA2 (1U << 10)
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#define SPC5_FLEXPWM_MASK_MASKA3 (1U << 11)
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/** @} */
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/**
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* @name MCTRL register bits definitions
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* @{
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*/
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#define SPC5_FLEXPWM_MCTRL_LDOK0 (1U << 0)
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#define SPC5_FLEXPWM_MCTRL_LDOK1 (1U << 1)
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#define SPC5_FLEXPWM_MCTRL_LODK2 (1U << 2)
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#define SPC5_FLEXPWM_MCTRL_LDOK3 (1U << 3)
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#define SPC5_FLEXPWM_MCTRL_CLDOK0 (1U << 4)
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#define SPC5_FLEXPWM_MCTRL_CLDOK1 (1U << 5)
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#define SPC5_FLEXPWM_MCTRL_CLDOK2 (1U << 6)
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#define SPC5_FLEXPWM_MCTRL_CLDOK3 (1U << 7)
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#define SPC5_FLEXPWM_MCTRL_RUN0 (1U << 8)
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#define SPC5_FLEXPWM_MCTRL_RUN1 (1U << 9)
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#define SPC5_FLEXPWM_MCTRL_RUN2 (1U << 10)
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#define SPC5_FLEXPWM_MCTRL_RUN3 (1U << 11)
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#define SPC5_FLEXPWM_MCTRL_IPOL0 (1U << 12)
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#define SPC5_FLEXPWM_MCTRL_IPOL1 (1U << 13)
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#define SPC5_FLEXPWM_MCTRL_IPOL2 (1U << 14)
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#define SPC5_FLEXPWM_MCTRL_IPOL3 (1U << 15)
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/** @} */
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/**
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* @name PSC values definition
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* @{
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*/
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#define SPC5_FLEXPWM_PSC_1 0
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#define SPC5_FLEXPWM_PSC_2 SPC5_FLEXPWM_CNTL1_PRSC0
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#define SPC5_FLEXPWM_PSC_4 SPC5_FLEXPWM_CNTL1_PRSC1
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#define SPC5_FLEXPWM_PSC_8 SPC5_FLEXPWM_CNTL1_PRSC0 || \
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SPC5_FLEXPWM_CNTL1_PRSC1
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#define SPC5_FLEXPWM_PSC_16 SPC5_FLEXPWM_CNTL1_PRSC2
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#define SPC5_FLEXPWM_PSC_32 SPC5_FLEXPWM_CNTL1_PRSC0 || \
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SPC5_FLEXPWM_CNTL1_PRSC2
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#define SPC5_FLEXPWM_PSC_64 SPC5_FLEXPWM_CNTL1_PRSC1 || \
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SPC5_FLEXPWM_CNTL1_PRSC2
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#define SPC5_FLEXPWM_PSC_128 SPC5_FLEXPWM_CNTL1_PRSC0 || \
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SPC5_FLEXPWM_CNTL1_PRSC1 || \
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SPC5_FLEXPWM_CNTL1_PRSC2
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/** @} */
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/**
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* @name LDOK, CLDOK, RUN, IPOL masks definition
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* @{
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*/
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#define SPC5_FLEXPWM_LDOK_MASK 0x000F
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#define SPC5_FLEXPWM_CLDOK_MASK 0x00F0
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#define SPC5_FLEXPWM_RUN_MASK 0x0F00
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#define SPC5_FLEXPWM_IPOL_MASK 0xF000
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/** @} */
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/**
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