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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12772 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2019-04-27 08:15:51 +00:00
parent 2376c38058
commit d0d69b4608
8 changed files with 244 additions and 244 deletions
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4
os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
View File

@ -57,6 +57,8 @@
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
#elif defined(STM32G0XX)
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM2_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM2
#else
@ -82,6 +84,8 @@
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
#elif defined(STM32G0XX)
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM3
#else

196
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
View File

@ -313,80 +313,6 @@ static void set_error(SerialDriver *sdp, uint32_t isr) {
osalSysUnlockFromISR();
}
/**
* @brief Common IRQ handler.
*
* @param[in] sdp communication channel associated to the USART
*/
static void serve_interrupt(SerialDriver *sdp) {
USART_TypeDef *u = sdp->usart;
uint32_t cr1 = u->CR1;
uint32_t isr;
/* Reading and clearing status.*/
isr = u->ISR;
u->ICR = isr;
/* Error condition detection.*/
if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE))
set_error(sdp, isr);
/* Special case, LIN break detection.*/
if (isr & USART_ISR_LBDF) {
osalSysLockFromISR();
chnAddFlagsI(sdp, SD_BREAK_DETECTED);
osalSysUnlockFromISR();
}
/* Data available, note it is a while in order to handle two situations:
1) Another byte arrived after removing the previous one, this would cause
an extra interrupt to serve.
2) FIFO mode is enabled on devices that support it, we need to empty
the FIFO.*/
while (isr & USART_ISR_RXNE) {
osalSysLockFromISR();
sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
osalSysUnlockFromISR();
isr = u->ISR;
}
/* Transmission buffer empty, note it is a while in order to handle two
situations:
1) The data registers has been emptied immediately after writing it, this
would cause an extra interrupt to serve.
2) FIFO mode is enabled on devices that support it, we need to fill
the FIFO.*/
if (cr1 & USART_CR1_TXEIE) {
while (isr & USART_ISR_TXE) {
msg_t b;
osalSysLockFromISR();
b = oqGetI(&sdp->oqueue);
if (b < MSG_OK) {
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
u->CR1 = cr1 & ~USART_CR1_TXEIE;
osalSysUnlockFromISR();
break;
}
u->TDR = b;
osalSysUnlockFromISR();
isr = u->ISR;
}
}
/* Physical transmission end.*/
if ((cr1 & USART_CR1_TCIE) && (isr & USART_ISR_TC)) {
osalSysLockFromISR();
if (oqIsEmptyI(&sdp->oqueue)) {
chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
u->CR1 = cr1 & ~USART_CR1_TCIE;
}
osalSysUnlockFromISR();
}
}
#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
static void notify1(io_queue_t *qp) {
@ -464,6 +390,7 @@ static void notifylp1(io_queue_t *qp) {
/*===========================================================================*/
#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
#if !defined(STM32_USART1_SUPPRESS_ISR)
#if !defined(STM32_USART1_HANDLER)
#error "STM32_USART1_HANDLER not defined"
#endif
@ -476,13 +403,15 @@ OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD1);
sd_lld_serve_interrupt(&SD1);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
#if !defined(STM32_USART2_SUPPRESS_ISR)
#if !defined(STM32_USART2_HANDLER)
#error "STM32_USART2_HANDLER not defined"
#endif
@ -495,11 +424,12 @@ OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD2);
sd_lld_serve_interrupt(&SD2);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if defined(STM32_USART3_8_HANDLER)
#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
@ -515,22 +445,22 @@ OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if STM32_SERIAL_USE_USART3
serve_interrupt(&SD3);
sd_lld_serve_interrupt(&SD3);
#endif
#if STM32_SERIAL_USE_UART4
serve_interrupt(&SD4);
sd_lld_serve_interrupt(&SD4);
#endif
#if STM32_SERIAL_USE_UART5
serve_interrupt(&SD5);
sd_lld_serve_interrupt(&SD5);
#endif
#if STM32_SERIAL_USE_USART6
serve_interrupt(&SD6);
sd_lld_serve_interrupt(&SD6);
#endif
#if STM32_SERIAL_USE_UART7
serve_interrupt(&SD7);
sd_lld_serve_interrupt(&SD7);
#endif
#if STM32_SERIAL_USE_UART8
serve_interrupt(&SD8);
sd_lld_serve_interrupt(&SD8);
#endif
OSAL_IRQ_EPILOGUE();
@ -540,6 +470,7 @@ OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) {
#else /* !defined(STM32_USART3_8_HANDLER) */
#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if !defined(STM32_USART3_SUPPRESS_ISR)
#if !defined(STM32_USART3_HANDLER)
#error "STM32_USART3_HANDLER not defined"
#endif
@ -552,13 +483,15 @@ OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD3);
sd_lld_serve_interrupt(&SD3);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
#if !defined(STM32_UART4_SUPPRESS_ISR)
#if !defined(STM32_UART4_HANDLER)
#error "STM32_UART4_HANDLER not defined"
#endif
@ -571,13 +504,15 @@ OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD4);
sd_lld_serve_interrupt(&SD4);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
#if !defined(STM32_UART5_SUPPRESS_ISR)
#if !defined(STM32_UART5_HANDLER)
#error "STM32_UART5_HANDLER not defined"
#endif
@ -590,13 +525,15 @@ OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD5);
sd_lld_serve_interrupt(&SD5);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
#if !defined(STM32_USART6_SUPPRESS_ISR)
#if !defined(STM32_USART6_HANDLER)
#error "STM32_USART6_HANDLER not defined"
#endif
@ -609,13 +546,15 @@ OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD6);
sd_lld_serve_interrupt(&SD6);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
#if !defined(STM32_UART7_SUPPRESS_ISR)
#if !defined(STM32_UART7_HANDLER)
#error "STM32_UART7_HANDLER not defined"
#endif
@ -628,13 +567,15 @@ OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD7);
sd_lld_serve_interrupt(&SD7);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
#if !defined(STM32_UART8_SUPPRESS_ISR)
#if !defined(STM32_UART8_HANDLER)
#error "STM32_UART8_HANDLER not defined"
#endif
@ -647,15 +588,17 @@ OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD8);
sd_lld_serve_interrupt(&SD8);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
#endif /* !defined(STM32_USART3_8_HANDLER) */
#if STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
#if !defined(STM32_LPUART1_SUPPRESS_ISR)
#if !defined(STM32_LPUART1_HANDLER)
#error "STM32_LPUART1_HANDLER not defined"
#endif
@ -668,11 +611,12 @@ OSAL_IRQ_HANDLER(STM32_LPUART1_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&LPSD1);
sd_lld_serve_interrupt(&LPSD1);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif
/*===========================================================================*/
/* Driver exported functions. */
@ -930,6 +874,80 @@ void sd_lld_stop(SerialDriver *sdp) {
}
}
/**
* @brief Common IRQ handler.
*
* @param[in] sdp communication channel associated to the USART
*/
void sd_lld_serve_interrupt(SerialDriver *sdp) {
USART_TypeDef *u = sdp->usart;
uint32_t cr1 = u->CR1;
uint32_t isr;
/* Reading and clearing status.*/
isr = u->ISR;
u->ICR = isr;
/* Error condition detection.*/
if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE))
set_error(sdp, isr);
/* Special case, LIN break detection.*/
if (isr & USART_ISR_LBDF) {
osalSysLockFromISR();
chnAddFlagsI(sdp, SD_BREAK_DETECTED);
osalSysUnlockFromISR();
}
/* Data available, note it is a while in order to handle two situations:
1) Another byte arrived after removing the previous one, this would cause
an extra interrupt to serve.
2) FIFO mode is enabled on devices that support it, we need to empty
the FIFO.*/
while (isr & USART_ISR_RXNE) {
osalSysLockFromISR();
sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
osalSysUnlockFromISR();
isr = u->ISR;
}
/* Transmission buffer empty, note it is a while in order to handle two
situations:
1) The data registers has been emptied immediately after writing it, this
would cause an extra interrupt to serve.
2) FIFO mode is enabled on devices that support it, we need to fill
the FIFO.*/
if (cr1 & USART_CR1_TXEIE) {
while (isr & USART_ISR_TXE) {
msg_t b;
osalSysLockFromISR();
b = oqGetI(&sdp->oqueue);
if (b < MSG_OK) {
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
u->CR1 = cr1 & ~USART_CR1_TXEIE;
osalSysUnlockFromISR();
break;
}
u->TDR = b;
osalSysUnlockFromISR();
isr = u->ISR;
}
}
/* Physical transmission end.*/
if ((cr1 & USART_CR1_TCIE) && (isr & USART_ISR_TC)) {
osalSysLockFromISR();
if (oqIsEmptyI(&sdp->oqueue)) {
chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
u->CR1 = cr1 & ~USART_CR1_TCIE;
}
osalSysUnlockFromISR();
}
}
#endif /* HAL_USE_SERIAL */
/** @} */

1
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
View File

@ -534,6 +534,7 @@ extern "C" {
void sd_lld_init(void);
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
void sd_lld_stop(SerialDriver *sdp);
void sd_lld_serve_interrupt(SerialDriver *sdp);
#ifdef __cplusplus
}
#endif

164
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -73,14 +73,6 @@ static void hal_lld_backup_domain_init(void) {
; /* Wait until LSE is stable. */
#endif
#if STM32_MSIPLL_ENABLED
/* MSI PLL activation depends on LSE. Reactivating and checking for
MSI stability.*/
RCC->CR |= RCC_CR_MSIPLLEN;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
#endif
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
@ -115,12 +107,9 @@ void hal_lld_init(void) {
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
rccResetAHB3(~0);
rccResetAPB1R1(~RCC_APB1RSTR1_PWRRST);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
rccResetAHB(~0);
rccResetAPBR1(~RCC_APBRSTR1_PWRRST);
rccResetAPBR2(~0);
/* PWR clock enabled.*/
rccEnablePWRInterface(true);
@ -136,22 +125,8 @@ void hal_lld_init(void) {
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
#else
PWR->CR2 = 0;
#endif /* STM32_PVD_ENABLE */
/* Enabling independent VDDUSB.*/
#if HAL_USE_USB
PWR->CR2 |= PWR_CR2_USV;
#endif /* HAL_USE_USB */
/* Enabling independent VDDIO2 required by GPIOG.*/
#if STM32_HAS_GPIOG
PWR->CR2 |= PWR_CR2_IOSV;
#endif /* STM32_HAS_GPIOG */
/* Programmable voltage detector settings.*/
PWR->CR2 = STM32_PWR_CR2;
}
/**
@ -165,34 +140,17 @@ void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
RCC->APBENR1 = RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN;
#else
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
RCC->APBENR1 = RCC_APBENR1_PWREN;
#endif
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
Trim fields are not altered from reset values.*/
/* MSIRANGE can be set only when MSI is OFF or READY.*/
RCC->CR = RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = 0;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
; /* Wait until MSI is selected. */
/* Core voltage setup.*/
PWR->CR1 = STM32_VOS;
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
; /* stable. */
/* Boost mode setting.*/
PWR->CR5 = STM32_R1MODE;
#if STM32_HSI16_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
@ -200,13 +158,6 @@ void stm32_clock_init(void) {
; /* Wait until HSI16 is stable. */
#endif
#if STM32_HSI48_ENABLED
/* HSI activation.*/
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
; /* Wait until HSI48 is stable. */
#endif
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
@ -241,38 +192,13 @@ void stm32_clock_init(void) {
; /* Wait until LSE is stable. */
#endif
/* Flash setup for selected MSI speed setting.*/
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_MSI_FLASHBITS;
/* Changing MSIRANGE to configured value.*/
RCC->CR |= STM32_MSIRANGE;
/* Switching from MSISRANGE to MSIRANGE.*/
RCC->CR |= RCC_CR_MSIRGSEL;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
;
/* MSI is configured SYSCLK source so wait for it to be stable as well.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
;
#if STM32_MSIPLL_ENABLED
/* MSI PLL (to LSE) activation */
RCC->CR |= RCC_CR_MSIPLLEN;
#endif
/* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high.
This range is used exiting the Standby mode until MSIRGSEL is set.*/
RCC->CSR |= STM32_MSISRANGE;
#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
#if STM32_ACTIVATE_PLL
/* PLLM and PLLSRC are common to all PLLs.*/
RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR |
STM32_PLLREN | STM32_PLLQ |
STM32_PLLQEN | STM32_PLLP |
STM32_PLLPEN | STM32_PLLN |
STM32_PLLM | STM32_PLLSRC;
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
#if STM32_ACTIVATE_PLL
@ -284,75 +210,33 @@ void stm32_clock_init(void) {
;
#endif
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
STM32_PLLSAI1REN | STM32_PLLSAI1Q |
STM32_PLLSAI1QEN | STM32_PLLSAI1P |
STM32_PLLSAI1PEN | STM32_PLLSAI1N |
STM32_PLLSAI1M;
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
;
#endif
#if STM32_ACTIVATE_PLLSAI2
/* PLLSAI2 activation.*/
RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
STM32_PLLSAI2REN | STM32_PLLSAI2P |
STM32_PLLSAI2PEN | STM32_PLLSAI2N |
STM32_PLLSAI2M;
RCC->CR |= RCC_CR_PLLSAI2ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0)
;
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = STM32_DFSDMSEL | STM32_ADCSEL |
STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
ccipr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
}
RCC->CCIPR = STM32_ADCSEL | STM32_RNGDIV | STM32_RNGSEL |
STM32_TIM15SEL | STM32_TIM1SEL | STM32_LPTIM2SEL |
STM32_LPTIM1SEL | STM32_I2S1SEL | STM32_I2C1SEL |
STM32_CECSEL | STM32_USART2SEL | STM32_USART1SEL |
STM32_LPUART1SEL;;
/* Set flash WS's for SYSCLK source */
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;
/* Switching to the configured SYSCLK source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
/* Switching to the configured SYSCLK source if it is different from HSI16.*/
#if STM32_SW != STM32_SW_HSISYS
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
/* Wait until SYSCLK is stable.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, true);
}
/** @} */

27
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -63,8 +63,8 @@
/**
* @brief Sub-family identifier.
*/
#if !defined(STM32G0xx) || defined(__DOXYGEN__)
#define STM32G0xx
#if !defined(STM32G0XX) || defined(__DOXYGEN__)
#define STM32G0XX
#endif
/** @} */
@ -1325,6 +1325,21 @@
#error "invalid source selected for USART2 clock"
#endif
/**
* @brief USART3 frequency.
*/
#define STM32_USART3CLK STM32_PCLK
/**
* @brief UART4 frequency.
*/
#define STM32_UART4CLK STM32_PCLK
/**
* @brief UART5 frequency.
*/
#define STM32_UART5CLK STM32_PCLK
/**
* @brief LPUART1 clock frequency.
*/
@ -1497,16 +1512,16 @@
* @brief Flash settings.
*/
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
#define STM32_FLASHBITS 0
#elif STM32_HCLK <= STM32_1WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
#define STM32_FLASHBITS FLASH_ACR_LATENCY_0
#elif STM32_HCLK <= STM32_2WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
#define STM32_FLASHBITS FLASH_ACR_LATENCY_1
#else
#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
#define STM32_FLASHBITS (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)
#endif
/*===========================================================================*/

32
os/hal/ports/STM32/STM32G0xx/stm32_isr.c
View File

@ -129,9 +129,33 @@ OSAL_IRQ_HANDLER(Vector5C) {
OSAL_IRQ_EPILOGUE();
}
#endif
#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
STM32_SERIAL_USE_LPUART1 || defined(__DOXYGEN__)
/**
* @brief USART3, USART4 and LPUART1 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_USART3_4_LP1_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if STM32_SERIAL_USE_USART3
sd_lld_serve_interrupt(&SD3);
#endif
#if STM32_SERIAL_USE_UART4
sd_lld_serve_interrupt(&SD4);
#endif
#if STM32_SERIAL_USE_LPUART1
sd_lld_serve_interrupt(&LPSD1);
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -148,6 +172,9 @@ void irqInit(void) {
nvicEnableVector(EXTI2_3_IRQn, STM32_IRQ_EXTI2_3_PRIORITY);
nvicEnableVector(EXTI4_15_IRQn, STM32_IRQ_EXTI4_15_PRIORITY);
#endif
#if HAL_USE_SERIAL
nvicEnableVector(USART3_4_LPUART1_IRQn, STM32_IRQ_USART3_4_LP1_PRIORITY);
#endif
}
/**
@ -162,6 +189,9 @@ void irqDeinit(void) {
nvicDisableVector(EXTI2_3_IRQn);
nvicDisableVector(EXTI4_15_IRQn);
#endif
#if HAL_USE_SERIAL
nvicDisableVector(USART3_4_LPUART1_IRQn);
#endif
}
/** @} */

52
os/hal/ports/STM32/STM32G0xx/stm32_isr.h
View File

@ -29,6 +29,15 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_USART3_SUPPRESS_ISR
#define STM32_UART4_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers remapping
* @{
@ -72,11 +81,11 @@
*/
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART3_8_LP1_HANDLER VectorB4
#define STM32_USART3_4_LP1_HANDLER VectorB4
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
#define STM32_USART3_8_LP1_NUMBER 29
#define STM32_USART3_4_LP1_NUMBER 29
/*
* USB units.
@ -122,12 +131,51 @@
#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI16_PRIORITY 3
#endif
/**
* @brief EXTI17..18 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI17_18_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI17_18_PRIORITY 3
#endif
/**
* @brief EXTI17..18 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_USART3_4_LP1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_USART3_4_LP1_PRIORITY 3
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* IRQ priority checks.*/
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_1_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_3_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_3_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_15_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_15_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_18_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_18_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART3_4_LP1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_USART3_4_LP1_PRIORITY"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

12
os/hal/ports/STM32/STM32G0xx/stm32_rcc.h
View File

@ -785,21 +785,21 @@
*
* @api
*/
#define rccEnableUART4(lp) rccEnableAPBR1(RCC_APBENR1_UART4EN, lp)
#define rccEnableUART4(lp) rccEnableAPBR1(RCC_APBENR1_USART4EN, lp)
/**
* @brief Disables the UART4 peripheral clock.
*
* @api
*/
#define rccDisableUART4() rccDisableAPBR1(RCC_APBENR1_UART4EN)
#define rccDisableUART4() rccDisableAPBR1(RCC_APBENR1_USART4EN)
/**
* @brief Resets the UART4 peripheral.
*
* @api
*/
#define rccResetUART4() rccResetAPBR1(RCC_APBRSTR1_UART4RST)
#define rccResetUART4() rccResetAPBR1(RCC_APBRSTR1_USART4RST)
/**
* @brief Enables the LPUART1 peripheral clock.
@ -808,21 +808,21 @@
*
* @api
*/
#define rccEnableLPUART1(lp) rccEnableAPBR2(RCC_APBENR2_LPUART1EN, lp)
#define rccEnableLPUART1(lp) rccEnableAPBR1(RCC_APBENR1_LPTIM2EN, lp)
/**
* @brief Disables the LPUART1 peripheral clock.
*
* @api
*/
#define rccDisableLPUART1() rccDisableAPBR2(RCC_APBENR2_LPUART1EN)
#define rccDisableLPUART1() rccDisableAPBR1(RCC_APBENR1_LPTIM2EN)
/**
* @brief Resets the USART1 peripheral.
*
* @api
*/
#define rccResetLPUART1() rccResetAPBR2(RCC_APBRSTR2_LPUART1RST)
#define rccResetLPUART1() rccResetAPBR1(RCC_APBRSTR1_LPUART1RST)
/** @} */
/**