Added section attributes to ld MEMORY sections.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12998 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-09-18 07:21:57 +00:00
parent f081b654b3
commit d369435bc4
73 changed files with 1146 additions and 1146 deletions

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@ -19,8 +19,8 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x080F8000, len = 32k flash0 (rx) : org = 0x080F8000, len = 32k
ram0 : org = 0x20017000, len = 4k ram0 (wx) : org = 0x20017000, len = 4k
} }
/* Flash region to be used for exception vectors.*/ /* Flash region to be used for exception vectors.*/

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M - 32k flash0 (rx) : org = 0x08000000, len = 1M - 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x08000000 + 1M - 32k, len = 32k flash7 (rx) : org = 0x08000000 + 1M - 32k, len = 32k
ram0 : org = 0x20000000, len = 96k - 4k ram0 (wx) : org = 0x20000000, len = 96k - 4k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 32k ram4 (wx) : org = 0x10000000, len = 32k
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x20000000 + 96k - 4k, len = 4k ram7 (wx) : org = 0x20000000 + 96k - 4k, len = 4k
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 16k flash0 (rx) : org = 0x08000000, len = 16k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 4k ram0 (wx) : org = 0x20000000, len = 4k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 4k ram0 (wx) : org = 0x20000000, len = 4k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 4k ram0 (wx) : org = 0x20000000, len = 4k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 6k ram0 (wx) : org = 0x20000000, len = 6k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 6k ram0 (wx) : org = 0x20000000, len = 6k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

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@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 16k ram0 (wx) : org = 0x20000000, len = 16k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 16k ram0 (wx) : org = 0x20000000, len = 16k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 32k ram0 (wx) : org = 0x20000000, len = 32k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 20k ram0 (wx) : org = 0x20000000, len = 20k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 20k ram0 (wx) : org = 0x20000000, len = 20k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -22,22 +22,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08005000, len = 128k - 0x5000 flash0 (rx) : org = 0x08005000, len = 128k - 0x5000
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000C00, len = 20k - 0xC00 ram0 (wx) : org = 0x20000C00, len = 20k - 0xC00
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 384k flash0 (rx) : org = 0x08000000, len = 384k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 96k ram0 (wx) : org = 0x20000000, len = 96k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0} ram7 (wx) : org = 0x00000000, len = 0}
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/ and a load region (_LMA suffix).*/

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 16k ram0 (wx) : org = 0x20000000, len = 16k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 12k ram0 (wx) : org = 0x20000000, len = 12k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 4k ram4 (wx) : org = 0x10000000, len = 4k
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 40k ram0 (wx) : org = 0x20000000, len = 40k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 8k ram4 (wx) : org = 0x10000000, len = 8k
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 16k ram4 (wx) : org = 0x10000000, len = 16k
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 12k ram0 (wx) : org = 0x20000000, len = 12k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 4k ram4 (wx) : org = 0x10000000, len = 4k
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 32k ram0 (wx) : org = 0x20000000, len = 32k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 96k ram0 (wx) : org = 0x20000000, len = 96k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 32k ram0 (wx) : org = 0x20000000, len = 32k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 32k ram0 (wx) : org = 0x20000000, len = 32k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k ram0 (wx) : org = 0x20000000, len = 128k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k ram0 (wx) : org = 0x20000000, len = 128k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 256k ram0 (wx) : org = 0x20000000, len = 256k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 256k ram0 (wx) : org = 0x20000000, len = 256k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1536k /* Program memory */ flash0 (rx) : org = 0x08000000, len = 1536k /* Program memory */
flash1 : org = 0x1FFF7800, len = 528 /* OTP memory */ flash1 (rx) : org = 0x1FFF7800, len = 528 /* OTP memory */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 320k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 320k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 256k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 256k /* SRAM1 */
ram2 : org = 0x20040000, len = 64k /* SRAM2 */ ram2 (wx) : org = 0x20040000, len = 64k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 64k /* CCM SRAM2 */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM2 */
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ ram0 (wx) : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */ ram3 (wx) : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x00000000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x00000000, len = 16k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x00000000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x00000000, len = 16k /* SRAM2 */
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -20,22 +20,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */ ram0 (wx) : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 160k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 160k /* SRAM1 */
ram2 : org = 0x20028000, len = 32k /* SRAM2 */ ram2 (wx) : org = 0x20028000, len = 32k /* SRAM2 */
ram3 : org = 0x20030000, len = 128k /* SRAM3 */ ram3 (wx) : org = 0x20030000, len = 128k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -25,22 +25,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20010000, len = 192k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20010000, len = 192k /* SRAM1 + SRAM2 */
ram1 : org = 0x20010000, len = 176k /* SRAM1 */ ram1 (wx) : org = 0x20010000, len = 176k /* SRAM1 */
ram2 : org = 0x2003C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2003C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -33,14 +33,14 @@ MEMORY
flash5 (RX) : org = 0x00000000, len = 0 flash5 (RX) : org = 0x00000000, len = 0
flash6 (RX) : org = 0x00000000, len = 0 flash6 (RX) : org = 0x00000000, len = 0
flash7 (RX) : org = 0x00000000, len = 0 flash7 (RX) : org = 0x00000000, len = 0
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
ram1 : org = 0x20010000, len = 240k /* SRAM1 */ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -26,22 +26,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
ram1 : org = 0x20010000, len = 240k /* SRAM1 */ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -27,22 +27,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
ram1 : org = 0x20010000, len = 240k /* SRAM1 */ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -25,22 +25,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
ram1 : org = 0x20010000, len = 240k /* SRAM1 */ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -25,22 +25,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
ram1 : org = 0x20020000, len = 368k /* SRAM1 */ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */
ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -25,22 +25,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */ flash0 (rx) : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */
flash1 : org = 0x00200000, len = 2M /* Flash as ITCM */ flash1 (rx) : org = 0x00200000, len = 2M /* Flash as ITCM */
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
ram1 : org = 0x20020000, len = 368k /* SRAM1 */ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */
ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */
ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 36k ram0 (wx) : org = 0x20000000, len = 36k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -27,22 +27,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 2M /* Flash bank1+bank2 */ flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */
flash1 : org = 0x08000000, len = 1M /* Flash bank 1 */ flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */
flash2 : org = 0x08100000, len = 1M /* Flash bank 2 */ flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x24000000, len = 512k /* AXI SRAM */ ram0 (wx) : org = 0x24000000, len = 512k /* AXI SRAM */
ram1 : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */ ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
ram2 : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */ ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
ram3 : org = 0x30040000, len = 32k /* AHB SRAM3 */ ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */
ram4 : org = 0x38000000, len = 64k /* AHB SRAM4 */ ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */
ram5 : org = 0x20000000, len = 128k /* DTCM-RAM */ ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram6 : org = 0x00000000, len = 64k /* ITCM-RAM */ ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
ram7 : org = 0x38800000, len = 4k /* BCKP SRAM */ ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 8k flash0 (rx) : org = 0x08000000, len = 8k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 2k ram0 (wx) : org = 0x20000000, len = 2k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 16k flash0 (rx) : org = 0x08000000, len = 16k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 2k ram0 (wx) : org = 0x20000000, len = 2k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 16k flash0 (rx) : org = 0x08000000, len = 16k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 16k flash0 (rx) : org = 0x08000000, len = 16k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 8k ram0 (wx) : org = 0x20000000, len = 8k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 64k flash0 (rx) : org = 0x08000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 20k ram0 (wx) : org = 0x20000000, len = 20k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 20k ram0 (wx) : org = 0x20000000, len = 20k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 192k flash0 (rx) : org = 0x08000000, len = 192k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 20k ram0 (wx) : org = 0x20000000, len = 20k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 32k flash0 (rx) : org = 0x08000000, len = 32k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 10k ram0 (wx) : org = 0x20000000, len = 10k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 16k ram0 (wx) : org = 0x20000000, len = 16k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 80k ram0 (wx) : org = 0x20000000, len = 80k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 128k flash0 (rx) : org = 0x08000000, len = 128k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 256k flash0 (rx) : org = 0x08000000, len = 256k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k ram0 (wx) : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 512k flash0 (rx) : org = 0x08000000, len = 512k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 128k ram0 (wx) : org = 0x20000000, len = 128k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 32k /* This memory also mapped at address 0x20020000 */ ram4 (wx) : org = 0x10000000, len = 32k /* This memory also mapped at address 0x20020000 */
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 96k ram0 (wx) : org = 0x20000000, len = 96k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 32k ram4 (wx) : org = 0x10000000, len = 32k
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 1M flash0 (rx) : org = 0x08000000, len = 1M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 256k ram0 (wx) : org = 0x20000000, len = 256k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x10000000, len = 64k /* This memory also mapped at address 0x20040000 */ ram4 (wx) : org = 0x10000000, len = 64k /* This memory also mapped at address 0x20040000 */
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 2M flash0 (rx) : org = 0x08000000, len = 2M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */ ram0 (wx) : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
ram1 : org = 0x20000000, len = 192k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 192k /* SRAM1 */
ram2 : org = 0x00000000, len = 64k /* SRAM2 */ ram2 (wx) : org = 0x00000000, len = 64k /* SRAM2 */
ram3 : org = 0x00000000, len = 384k /* SRAM3 */ ram3 (wx) : org = 0x00000000, len = 384k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* SRAM2 alias */ ram4 (wx) : org = 0x10000000, len = 64k /* SRAM2 alias */
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

View File

@ -19,22 +19,22 @@
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x08000000, len = 2M flash0 (rx) : org = 0x08000000, len = 2M
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */ ram0 (wx) : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
ram1 : org = 0x20000000, len = 192k /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = 192k /* SRAM1 */
ram2 : org = 0x00000000, len = 64k /* SRAM2 */ ram2 (wx) : org = 0x00000000, len = 64k /* SRAM2 */
ram3 : org = 0x00000000, len = 384k /* SRAM3 */ ram3 (wx) : org = 0x00000000, len = 384k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* SRAM2 alias */ ram4 (wx) : org = 0x10000000, len = 64k /* SRAM2 alias */
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region