mirror of https://github.com/rusefi/ChibiOS.git
Fixed bug #1000.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12538 110e8d01-0319-4d1e-a829-52ad28d1bb01
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@ -800,7 +800,7 @@
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* @note The allowed values are 2..128, odd values not allowed.
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* @note The allowed values are 2..128, odd values not allowed.
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*/
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*/
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#if !defined(STM32_PLL2_DIVP_VALUE) || defined(__DOXYGEN__)
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#if !defined(STM32_PLL2_DIVP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL2_DIVP_VALUE 8
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#define STM32_PLL2_DIVP_VALUE 40
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#endif
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#endif
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/**
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/**
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@ -860,7 +860,7 @@
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* @note The allowed values are 4..512.
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* @note The allowed values are 4..512.
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*/
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*/
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#if !defined(STM32_PLL3_DIVN_VALUE) || defined(__DOXYGEN__)
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#if !defined(STM32_PLL3_DIVN_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3_DIVN_VALUE 240
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#define STM32_PLL3_DIVN_VALUE 400
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#endif
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#endif
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/**
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/**
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@ -876,7 +876,7 @@
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* @note The allowed values are 2..128, odd values not allowed.
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* @note The allowed values are 2..128, odd values not allowed.
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*/
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*/
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#if !defined(STM32_PLL3_DIVP_VALUE) || defined(__DOXYGEN__)
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#if !defined(STM32_PLL3_DIVP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3_DIVP_VALUE 10
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#define STM32_PLL3_DIVP_VALUE 8
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#endif
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#endif
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/**
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/**
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@ -884,7 +884,7 @@
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* @note The allowed values are 1..128.
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* @note The allowed values are 1..128.
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*/
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*/
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#if !defined(STM32_PLL3_DIVQ_VALUE) || defined(__DOXYGEN__)
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#if !defined(STM32_PLL3_DIVQ_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3_DIVQ_VALUE 10
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#define STM32_PLL3_DIVQ_VALUE 8
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#endif
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#endif
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/**
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/**
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@ -892,7 +892,7 @@
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* @note The allowed values are 1..128.
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* @note The allowed values are 1..128.
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*/
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*/
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#if !defined(STM32_PLL3_DIVR_VALUE) || defined(__DOXYGEN__)
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#if !defined(STM32_PLL3_DIVR_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3_DIVR_VALUE 10
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#define STM32_PLL3_DIVR_VALUE 8
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#endif
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#endif
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/**
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/**
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@ -2399,7 +2399,7 @@
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*/
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*/
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#define STM32_USART6CLK STM32_PCLK2
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#define STM32_USART6CLK STM32_PCLK2
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#elif STM32_USART1SEL == STM32_USART16SEL_PLL2_Q_CK
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#elif STM32_USART16SEL == STM32_USART16SEL_PLL2_Q_CK
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#define STM32_USART1CLK STM32_PLL2_Q_CK
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#define STM32_USART1CLK STM32_PLL2_Q_CK
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#define STM32_USART6CLK STM32_PLL2_Q_CK
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#define STM32_USART6CLK STM32_PLL2_Q_CK
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#elif STM32_USART16SEL == STM32_USART16SEL_PLL3_Q_CK
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#elif STM32_USART16SEL == STM32_USART16SEL_PLL3_Q_CK
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@ -2579,8 +2579,8 @@
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*/
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*/
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#define STM32_SPI6CLK STM32_PCLK4
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#define STM32_SPI6CLK STM32_PCLK4
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#elif STM32_SPI6SEL == STM32_SPI6SEL_PLL2_P_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_PLL2_Q_CK
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#define STM32_SPI6CLK STM32_PLL2_P_CK
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#define STM32_SPI6CLK STM32_PLL2_Q_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_PLL3_Q_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_PLL3_Q_CK
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#define STM32_SPI6CLK STM32_PLL3_Q_CK
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#define STM32_SPI6CLK STM32_PLL3_Q_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_HSI_KER_CK
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#elif STM32_SPI6SEL == STM32_SPI6SEL_HSI_KER_CK
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@ -196,6 +196,8 @@
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- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
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- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
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- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
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- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
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- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
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- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
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- HAL: Fixed invalid checks in STM32H7 HAL (bug #1000)
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(backported to 18.2.2).
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- OTH: Fixed problem in STM32H743 GCC linker file (bug #998)
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- OTH: Fixed problem in STM32H743 GCC linker file (bug #998)
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(backported to 18.2.2).
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(backported to 18.2.2).
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- HAL: Fixed extra parenthesis in STM32F4 registry (bug #997)
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- HAL: Fixed extra parenthesis in STM32F4 registry (bug #997)
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