mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12625 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio
parent
84757ac8a2
commit
d4e670fc44
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F4xx/stm32_isr.c
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* @brief STM32F4xx ISR handler code.
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*
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* @addtogroup STM32F4xx_ISR
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#define exti_serve_irq(pr, channel) { \
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\
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if ((pr) & (1U << (channel))) { \
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_pal_isr_code(channel); \
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} \
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
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#if !defined(STM32_DISABLE_EXTI0_HANDLER)
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/**
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* @brief EXTI[0] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector58) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 0);
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EXTI->PR = pr;
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exti_serve_irq(pr, 0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI1_HANDLER)
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/**
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* @brief EXTI[1] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector5C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 1);
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EXTI->PR = pr;
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exti_serve_irq(pr, 1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI2_HANDLER)
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/**
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* @brief EXTI[2] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector60) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 2);
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EXTI->PR = pr;
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exti_serve_irq(pr, 2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI3_HANDLER)
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/**
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* @brief EXTI[3] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector64) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 3);
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EXTI->PR = pr;
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exti_serve_irq(pr, 3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI4_HANDLER)
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/**
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* @brief EXTI[4] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector68) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 4);
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EXTI->PR = pr;
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exti_serve_irq(pr, 4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
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/**
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* @brief EXTI[5]...EXTI[9] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector9C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
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(1U << 9));
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EXTI->PR = pr;
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exti_serve_irq(pr, 5);
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exti_serve_irq(pr, 6);
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exti_serve_irq(pr, 7);
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exti_serve_irq(pr, 8);
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exti_serve_irq(pr, 9);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
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/**
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* @brief EXTI[10]...EXTI[15] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorE0) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
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(1U << 14) | (1U << 15));
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EXTI->PR = pr;
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exti_serve_irq(pr, 10);
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exti_serve_irq(pr, 11);
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exti_serve_irq(pr, 12);
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exti_serve_irq(pr, 13);
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exti_serve_irq(pr, 14);
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exti_serve_irq(pr, 15);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
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#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
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/**
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* @brief TIM1-BRK, TIM9 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorA0) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM9
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gpt_lld_serve_interrupt(&GPTD9);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM9
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icu_lld_serve_interrupt(&ICUD9);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM9
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pwm_lld_serve_interrupt(&PWMD9);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1-UP, TIM10 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorA4) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM1
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gpt_lld_serve_interrupt(&GPTD1);
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#endif
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#if STM32_GPT_USE_TIM10
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gpt_lld_serve_interrupt(&GPTD10);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM1
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icu_lld_serve_interrupt(&ICUD1);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM1
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pwm_lld_serve_interrupt(&PWMD1);
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#endif
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#if STM32_PWM_USE_TIM10
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pwm_lld_serve_interrupt(&PWMD10);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1-TRG-COM, TIM11 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorA8) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM11
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gpt_lld_serve_interrupt(&GPTD11);
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#endif
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#endif
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#if HAL_USE_ICU
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/* Not used by ICU.*/
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM11
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pwm_lld_serve_interrupt(&PWMD11);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1-CC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorAC) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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/* Not used by GPT.*/
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM1
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icu_lld_serve_interrupt(&ICUD1);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM1
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pwm_lld_serve_interrupt(&PWMD1);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-BRK, TIM12 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorEC) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM12
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gpt_lld_serve_interrupt(&GPTD12);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM12
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icu_lld_serve_interrupt(&ICUD12);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM12
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pwm_lld_serve_interrupt(&PWMD12);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-UP, TIM13 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorF0) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM8
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gpt_lld_serve_interrupt(&GPTD8);
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#endif
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#if STM32_GPT_USE_TIM13
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gpt_lld_serve_interrupt(&GPTD13);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM8
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icu_lld_serve_interrupt(&ICUD8);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM8
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pwm_lld_serve_interrupt(&PWMD8);
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#endif
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#if STM32_PWM_USE_TIM13
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pwm_lld_serve_interrupt(&PWMD13);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-TRG-COM, TIM14 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorF4) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM14
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gpt_lld_serve_interrupt(&GPTD14);
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#endif
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#endif
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#if HAL_USE_ICU
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/* Not used by ICU.*/
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM14
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pwm_lld_serve_interrupt(&PWMD14);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-CC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorF8) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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/* Not used by GPT.*/
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM8
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icu_lld_serve_interrupt(&ICUD8);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM8
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pwm_lld_serve_interrupt(&PWMD8);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */
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/*===========================================================================*/
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/* Driver exported functions. */
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||||
/*===========================================================================*/
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/**
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* @brief Enables IRQ sources.
|
||||
*
|
||||
* @notapi
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||||
*/
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void irqInit(void) {
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#if HAL_USE_PAL
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nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
|
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nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
|
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nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
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nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
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nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
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nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
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nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
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||||
#endif
|
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#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
|
||||
nvicEnableVector(TIM1_BRK_TIM9_IRQn, STM32_IRQ_TIM1_BRK_TIM9_PRIORITY);
|
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nvicEnableVector(TIM1_UP_TIM10_IRQn, STM32_IRQ_TIM1_UP_TIM10_PRIORITY);
|
||||
nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY);
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nvicEnableVector(TIM1_CC_IRQn, STM32_IRQ_TIM1_CC_PRIORITY);
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||||
nvicEnableVector(TIM8_BRK_TIM12_IRQn, STM32_IRQ_TIM8_BRK_TIM12_PRIORITY);
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nvicEnableVector(TIM8_UP_TIM13_IRQn, STM32_IRQ_TIM8_UP_TIM13_PRIORITY);
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||||
nvicEnableVector(TIM8_TRG_COM_TIM14_IRQn, STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY);
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||||
nvicEnableVector(TIM8_CC_IRQn, STM32_IRQ_TIM8_CC_PRIORITY);
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||||
#endif
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||||
}
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||||
/**
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||||
* @brief Disables IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
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||||
void irqDeinit(void) {
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#if HAL_USE_PAL
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nvicDisableVector(EXTI0_IRQn);
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||||
nvicDisableVector(EXTI1_IRQn);
|
||||
nvicDisableVector(EXTI2_IRQn);
|
||||
nvicDisableVector(EXTI3_IRQn);
|
||||
nvicDisableVector(EXTI4_IRQn);
|
||||
nvicDisableVector(EXTI9_5_IRQn);
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||||
nvicDisableVector(EXTI15_10_IRQn);
|
||||
#endif
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||||
#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
|
||||
nvicDisableVector(TIM1_BRK_TIM9_IRQn);
|
||||
nvicDisableVector(TIM1_UP_TIM10_IRQn);
|
||||
nvicDisableVector(TIM1_TRG_COM_TIM11_IRQn);
|
||||
nvicDisableVector(TIM1_CC_IRQn);
|
||||
nvicDisableVector(TIM8_BRK_TIM12_IRQn);
|
||||
nvicDisableVector(TIM8_UP_TIM13_IRQn);
|
||||
nvicDisableVector(TIM8_TRG_COM_TIM14_IRQn);
|
||||
nvicDisableVector(TIM8_CC_IRQn);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F4xx/stm32_isr.h
|
||||
* @brief STM32F4xx ISR handler header.
|
||||
*
|
||||
* @addtogroup STM32F4xx_ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef STM32_ISR_H
|
||||
#define STM32_ISR_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name ISR names and numbers remapping
|
||||
* @{
|
||||
*/
|
||||
#define STM32_TIM1_SUPPRESS_ISR
|
||||
#define STM32_TIM9_SUPPRESS_ISR
|
||||
#define STM32_TIM10_SUPPRESS_ISR
|
||||
#define STM32_TIM11_SUPPRESS_ISR
|
||||
#define STM32_TIM8_SUPPRESS_ISR
|
||||
#define STM32_TIM12_SUPPRESS_ISR
|
||||
#define STM32_TIM13_SUPPRESS_ISR
|
||||
#define STM32_TIM14_SUPPRESS_ISR
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI0 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI0_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI1_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI2_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI3_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI4_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI5..9 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI10..15 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI16 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI16_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI17 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI18 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI18_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI21 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI21_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI22 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI22_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI23 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI23_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI23_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* IRQ priority checks.*/
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI22_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI22_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI23_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI23_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM9_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM9_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM10_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM10_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_BRK_TIM12_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM12_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_UP_TIM13_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM13_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM14_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_CC_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void irqInit(void);
|
||||
void irqDeinit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_ISR_H */
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue