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Improved cache settings in STM32H7xx mcuconf.h. 

Modified SDMMCv2 to allow for uncached buffers.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15550 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-03-21 11:21:51 +00:00
parent b2f2f91972
commit d62c01ac48
24 changed files with 270 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
demos/STM32/NIL-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

4
demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -45,8 +45,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

4
demos/STM32/RT-STM32H735IG-DISCOVERY/cfg/mcuconf.h
View File

@ -45,8 +45,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
demos/STM32/RT-STM32H755ZI_M4-NUCLEO144/cfg/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

3
demos/STM32/RT-VFS-FATFS/.cproject
View File

@ -162,6 +162,9 @@
<scannerConfigBuildInfo instanceId="0.365230168.523175374.1281863608">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="0.365230168.523175374.18049993">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="0.365230168">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
</scannerConfigBuildInfo>

4
demos/STM32/RT-VFS-FATFS/cfg/stm32h735ig_discovery/mcuconf.h
View File

@ -45,8 +45,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE TRUE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

2
demos/STM32/RT-VFS-FATFS/make/stm32h735ig_discovery.make
View File

@ -122,7 +122,7 @@ include $(CHIBIOS)/os/various/shell/shell.mk
include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32H735xG_ITCM64k.ld
LDSCRIPT= $(STARTUPLD)/STM32H723xG_ITCM64k_AXI_NC.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.

138
os/common/startup/ARMCMx/compilers/GCC/ld/STM32H723xG_ITCM64k_AXI_NC.ld Normal file
View File

@ -0,0 +1,138 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32H723xG (64k ITCM) generic setup.
*
* AXI SRAM - BSS, Data, Heap.
* SRAM1+SRAM2 - NOCACHE, ETH.
* SRAM4 - None.
* DTCM-RAM - Main Stack, Process Stack.
* ITCM-RAM - None.
* BCKP SRAM - None.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 1M /* Flash bank1 */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x24000000, len = 16k /* AXI SRAM no-cache*/
ram1 (wx) : org = 0x24004000, len = 304k /* AXI SRAM cached */
ram2 (wx) : org = 0x30000000, len = 16k /* AHB SRAM1 */
ram3 (wx) : org = 0x30002000, len = 16k /* AHB SRAM2 */
ram4 (wx) : org = 0x38000000, len = 16k /* AHB SRAM4 */
ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram5);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram5);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram1);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram1);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram1);
/* Stack rules inclusion.*/
INCLUDE rules_stacks.ld
/*===========================================================================*/
/* Custom sections for STM32H7xx. */
/* SRAM3 is assumed to be marked non-cacheable using MPU. */
/*===========================================================================*/
/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram0);
/* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3);
SECTIONS
{
/* Special section for non cache-able areas.*/
.nocache (NOLOAD) : ALIGN(4)
{
__nocache_base__ = .;
*(.nocache)
*(.nocache.*)
*(.bss.__nocache_*)
. = ALIGN(4);
__nocache_end__ = .;
} > NOCACHE_RAM
/* Special section for Ethernet DMA non cache-able areas.*/
.eth (NOLOAD) : ALIGN(4)
{
__eth_base__ = .;
*(.eth)
*(.eth.*)
*(.bss.__eth_*)
. = ALIGN(4);
__eth_end__ = .;
} > ETH_RAM
}
/* Code rules inclusion.*/
INCLUDE rules_code.ld
/* Data rules inclusion.*/
INCLUDE rules_data.ld
/* Memory rules inclusion.*/
INCLUDE rules_memory.ld

30
os/hal/ports/STM32/LLD/SDMMCv2/hal_sdc_lld.c
View File

@ -64,6 +64,16 @@ static const SDCConfig sdc_default_cfg = {
SDC_MODE_4BIT
};
#if STM32_SDC_USE_SDMMC1 || defined(__DOXYGEN__)
static uint8_t __nocache_sd1_buf[MMCSD_BLOCK_SIZE];
static uint32_t __nocache_sd1_wbuf[1];
#endif
#if STM32_SDC_USE_SDMMC2 || defined(__DOXYGEN__)
static uint8_t __nocache_sd2_buf[MMCSD_BLOCK_SIZE];
static uint32_t __nocache_sd2_wbuf[1];
#endif
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@ -317,6 +327,8 @@ void sdc_lld_init(void) {
SDCD1.thread = NULL;
SDCD1.sdmmc = SDMMC1;
SDCD1.clkfreq = STM32_SDMMC1CLK;
SDCD1.buf = __nocache_sd1_buf;
SDCD1.resp = __nocache_sd1_wbuf;
#endif
#if STM32_SDC_USE_SDMMC2
@ -324,6 +336,8 @@ void sdc_lld_init(void) {
SDCD2.thread = NULL;
SDCD2.sdmmc = SDMMC2;
SDCD2.clkfreq = STM32_SDMMC2CLK;
SDCD2.buf = __nocache_sd2_buf;
SDCD2.resp = __nocache_sd2_wbuf;
#endif
}
@ -626,22 +640,21 @@ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
*/
bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
uint8_t cmd, uint32_t arg) {
uint32_t resp[1];
if (sdc_lld_prepare_read_bytes(sdcp, buf, bytes))
goto error;
if (sdc_lld_send_cmd_short_crc(sdcp, SDMMC_CMD_CMDTRANS | cmd, arg, resp) ||
MMCSD_R1_ERROR(resp[0]))
if (sdc_lld_send_cmd_short_crc(sdcp, SDMMC_CMD_CMDTRANS | cmd, arg, sdcp->resp) ||
MMCSD_R1_ERROR(sdcp->resp[0]))
goto error;
if (sdc_lld_wait_transaction_end(sdcp, 1, resp))
if (sdc_lld_wait_transaction_end(sdcp, 1, sdcp->resp))
goto error;
return HAL_SUCCESS;
error:
sdc_lld_error_cleanup(sdcp, 1, resp);
sdc_lld_error_cleanup(sdcp, 1, sdcp->resp);
return HAL_FAILED;
}
@ -661,7 +674,6 @@ error:
*/
bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
uint8_t *buf, uint32_t blocks) {
uint32_t resp[1];
osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE);
@ -688,16 +700,16 @@ bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
sdcp->sdmmc->IDMABASE0 = (uint32_t)buf;
sdcp->sdmmc->IDMACTRL = SDMMC_IDMA_IDMAEN;
if (sdc_lld_prepare_read(sdcp, startblk, blocks, resp) == true)
if (sdc_lld_prepare_read(sdcp, startblk, blocks, sdcp->resp) == true)
goto error;
if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == true)
if (sdc_lld_wait_transaction_end(sdcp, blocks, sdcp->resp) == true)
goto error;
return HAL_SUCCESS;
error:
sdc_lld_error_cleanup(sdcp, blocks, resp);
sdc_lld_error_cleanup(sdcp, blocks, sdcp->resp);
return HAL_FAILED;
}

8
os/hal/ports/STM32/LLD/SDMMCv2/hal_sdc_lld.h
View File

@ -227,6 +227,10 @@ struct SDCDriver {
* @brief Card RCA.
*/
uint32_t rca;
/**
* @brief Buffer of @p MMCSD_BLOCK_SIZE bytes for internal operations.
*/
uint8_t *buf;
/* End of the mandatory fields.*/
/**
* @brief Thread waiting for I/O completion IRQ.
@ -242,9 +246,9 @@ struct SDCDriver {
*/
uint32_t clkfreq;
/**
* @brief Buffer for internal operations.
* @brief Uncached word buffer for small transfers.
*/
uint8_t buf[MMCSD_BLOCK_SIZE];
uint32_t *resp;
};
/*===========================================================================*/

34
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -168,41 +168,15 @@ void hal_lld_init(void) {
/* IRQ subsystem initialization.*/
irqInit();
/* MPU initialization.*/
#if (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) || (STM32_NOCACHE_SRAM3 == TRUE)
/* MPU initialization if required.*/
#if STM32_NOCACHE_ENABLE == TRUE
{
uint32_t base, size;
#if defined(HAL_LLD_TYPE1_H)
#if (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) && (STM32_NOCACHE_SRAM3 == TRUE)
base = 0x30000000U;
size = MPU_RASR_SIZE_512K;
#elif (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) && (STM32_NOCACHE_SRAM3 == FALSE)
base = 0x30000000U;
size = MPU_RASR_SIZE_256K;
#elif (STM32_NOCACHE_SRAM1_SRAM2 == FALSE) && (STM32_NOCACHE_SRAM3 == TRUE)
base = 0x30040000U;
size = MPU_RASR_SIZE_32K;
#else
#error "invalid constants used in mcuconf.h"
#endif
#elif defined(HAL_LLD_TYPE2_H)
#if STM32_NOCACHE_SRAM3 == TRUE
#error "SRAM3 not present on this device"
#endif
base = 0x30000000U;
size = MPU_RASR_SIZE_32K;
#endif
/* The SRAM2 bank can optionally made a non cache-able area for use by
DMA engines.*/
mpuConfigureRegion(STM32_NOCACHE_MPU_REGION,
base,
STM32_NOCACHE_RBAR,
MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_NON_CACHEABLE |
MPU_RASR_ATTR_S |
size |
STM32_NOCACHE_RASR |
MPU_RASR_ENABLE);
mpuEnable(MPU_CTRL_PRIVDEFENA);

58
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -68,6 +68,13 @@
#define STM32_TARGET_CORE 1
#endif
/**
* @brief Enables a no-cache RAM area using the MPU.
*/
#if !defined(STM32_NOCACHE_ENABLE) || defined(__DOXYGEN__)
#define STM32_NOCACHE_ENABLE FALSE
#endif
/**
* @brief MPU region to be used for no-cache RAM area.
*/
@ -76,17 +83,17 @@
#endif
/**
* @brief Add no-cache attribute to SRAM1 and SRAM2.
* @brief Base address to be used for no-cache RAM area.
*/
#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#if !defined(STM32_NOCACHE_RBAR) || defined(__DOXYGEN__)
#define STM32_NOCACHE_RBAR 0x24000000U
#endif
/**
* @brief Add no-cache attribute to SRAM3.
* @brief Size to be used for no-cache RAM area.
*/
#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
#define STM32_NOCACHE_SRAM3 FALSE
#if !defined(STM32_NOCACHE_RASR) || defined(__DOXYGEN__)
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
#endif
/** @} */
@ -94,6 +101,42 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/* Various helpers.*/
#include "nvic.h"
#include "cache.h"
#include "mpu_v7m.h"
#if (STM32_NOCACHE_RASR != MPU_RASR_SIZE_32) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_64) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_128) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_256) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_512) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_1K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_2K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_4K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_8K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_16K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_32K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_64K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_128K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_256K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_512K) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_1M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_2M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_4M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_8M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_16M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_32M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_64M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_128M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_256M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_512M) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_1G) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_2G) && \
(STM32_NOCACHE_RASR != MPU_RASR_SIZE_4G)
#error "invalid MPU RASR size value"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -115,9 +158,6 @@
#endif
/* Various helpers.*/
#include "nvic.h"
#include "cache.h"
#include "mpu_v7m.h"
#include "stm32_isr.h"
#include "stm32_mdma.h"
#include "stm32_dma.h"

2
os/hal/src/hal_sdc.c
View File

@ -319,7 +319,7 @@ static bool sdc_cmd6_check_status(sd_switch_function_t function,
static bool sdc_detect_bus_clk(SDCDriver *sdcp, sdcbusclk_t *clk) {
uint32_t cmdarg;
const size_t N = 64;
uint8_t tmp[N];
uint8_t *tmp = sdcp->buf;
/* Safe default.*/
*clk = SDC_CLK_25MHz;

2
readme.txt
View File

@ -74,6 +74,8 @@
*****************************************************************************
*** Next ***
- NEW: Improved cache settings in STM32H7xx mcuconf.h.
- NEW: Modified SDMMCv2 to allow for uncached buffers.
- NEW: Added OCTOSPIv2 driver using MDMA for STM32H7xx.
- NEW: Added demos for STM32H723ZG Nucleo144 and STM32H735ZI Discovery boards.
- NEW: Added support for STM32H723/25/33/35.

5
testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

5
testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -50,9 +50,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE FALSE
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
#define STM32_NOCACHE_RBAR 0x24000000U
#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
/*
* PWR system settings.

4
tools/ftl/processors/conf/mcuconf_stm32h723xx/mcuconf.h.ftl
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@ -56,8 +56,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE ${doc.STM32_NOCACHE_ENABLE!"FALSE"}
#define STM32_NOCACHE_MPU_REGION ${doc.STM32_NOCACHE_MPU_REGION!"MPU_REGION_6"}
#define STM32_NOCACHE_SRAM1_SRAM2 ${doc.STM32_NOCACHE_SRAM1_SRAM2!"TRUE"}
#define STM32_NOCACHE_RBAR ${doc.STM32_NOCACHE_RBAR!"0x24000000U"}
#define STM32_NOCACHE_RASR ${doc.STM32_NOCACHE_RBAR!"MPU_RASR_SIZE_16K"}
/*
* PWR system settings.

5
tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
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@ -61,9 +61,10 @@
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_ENABLE ${doc.STM32_NOCACHE_ENABLE!"FALSE"}
#define STM32_NOCACHE_MPU_REGION ${doc.STM32_NOCACHE_MPU_REGION!"MPU_REGION_6"}
#define STM32_NOCACHE_SRAM1_SRAM2 ${doc.STM32_NOCACHE_SRAM1_SRAM2!"FALSE"}
#define STM32_NOCACHE_SRAM3 ${doc.STM32_NOCACHE_SRAM3!"TRUE"}
#define STM32_NOCACHE_RBAR ${doc.STM32_NOCACHE_RBAR!"0x24000000U"}
#define STM32_NOCACHE_RASR ${doc.STM32_NOCACHE_RBAR!"MPU_RASR_SIZE_16K"}
/*
* PWR system settings.