From d7f811f4dd233c2c66b91e0047e0dee9d352954d Mon Sep 17 00:00:00 2001 From: vrepetenko Date: Mon, 31 May 2021 18:47:38 +0000 Subject: [PATCH] STM32WL port: clock management updated, PWR_PUCRx/PWR_PDCRx conf/init added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14454 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h | 13 +++- os/hal/ports/STM32/STM32WLxx/hal_lld.c | 55 +++++++++------ os/hal/ports/STM32/STM32WLxx/hal_lld.h | 68 ++++++++++++++++++- 3 files changed, 112 insertions(+), 24 deletions(-) diff --git a/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h index 0cbd9e78d..8c78dcd89 100644 --- a/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h @@ -39,8 +39,15 @@ #define STM32_NO_INIT FALSE #define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 +#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0 | PWR_CR2_PVDE) +#define STM32_PWR_PUCRA (0U) +#define STM32_PWR_PDCRA (0U) +#define STM32_PWR_PUCRB (0U) +#define STM32_PWR_PDCRB (0U) +#define STM32_PWR_PUCRC (0U) +#define STM32_PWR_PDCRC (0U) +#define STM32_PWR_PUCRH (0U) +#define STM32_PWR_PDCRH (0U) #define STM32_HSI16_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_LSIPRE STM32_LSIPRE_NODIV @@ -65,7 +72,7 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0 | PWR_CR2_PVDE) + /* * Peripherals clock sources. diff --git a/os/hal/ports/STM32/STM32WLxx/hal_lld.c b/os/hal/ports/STM32/STM32WLxx/hal_lld.c index 2084f0e03..d33411be5 100644 --- a/os/hal/ports/STM32/STM32WLxx/hal_lld.c +++ b/os/hal/ports/STM32/STM32WLxx/hal_lld.c @@ -43,6 +43,14 @@ */ #define STM32_RCC_CR_RESET 0x00000061U +/** + * @brief PWR CR bits safe for fast switch. + */ +#define STM32_PWR_CR1_SAFE_ONLY_MASK (PWR_CR1_LPR | \ + PWR_CR1_FPDS | \ + PWR_CR1_SUBGHZSPINSSSEL | \ + PWR_CR1_LPMS_Msk) + /** * @brief MSI range array size. */ @@ -65,8 +73,6 @@ uint32_t SystemCoreClock = STM32_HCLK; const halclkcfg_t hal_clkcfg_reset = { .pwr_cr1 = PWR_CR1_VOS_0, .pwr_cr2 = 0U, - .pwr_cr3 = PWR_CR3_EWRFBUSY, - .pwr_cr4 = 0U, .rcc_cr = RCC_CR_MSIRANGE_6 | RCC_CR_MSION, .rcc_cfgr = RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF, .rcc_extcfgr = 0U, @@ -80,8 +86,6 @@ const halclkcfg_t hal_clkcfg_reset = { const halclkcfg_t hal_clkcfg_default = { .pwr_cr1 = STM32_VOS | PWR_CR1_DBP, .pwr_cr2 = STM32_PWR_CR2, - .pwr_cr3 = STM32_PWR_CR3, - .pwr_cr4 = STM32_PWR_CR4, .rcc_cr = RCC_CR_MSIRANGE_6 | RCC_CR_MSION #if STM32_HSI16_ENABLED | RCC_CR_HSIKERON | RCC_CR_HSION @@ -463,23 +467,21 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) { return false; } + /** - * @brief Switches to a different clock configuration. + * @brief Configures full clock settings. * * @param[in] ccp pointer to clock a @p halclkcfg_t structure - * @return The clock switch result. + * @return The clock configuration result. * @retval false if the clock switch succeeded * @retval true if the clock switch failed * * @notapi */ -bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) { +bool hal_lld_clock_raw_config(const halclkcfg_t *ccp) { /* Restoring default PWR settings related clocks and sleep modes.*/ PWR->CR1 = PWR_CR1_VOS_0; - PWR->CR2 = 0U; - PWR->CR3 = PWR_CR3_EWRFBUSY; - PWR->CR4 = 0U; /* Waiting for all regulator status bits to be cleared, this means that power levels are stable.*/ @@ -533,20 +535,16 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) { /* Final PWR modes.*/ PWR->CR1 = ccp->pwr_cr1; PWR->CR2 = ccp->pwr_cr2; - PWR->CR3 = ccp->pwr_cr3; - PWR->CR4 = ccp->pwr_cr4; /* Waiting for the correct regulator state.*/ if ((ccp->pwr_cr1 & PWR_CR1_LPR) == 0U) { /* Main mode selected.*/ - while ((PWR->SR2 & PWR_SR2_REGLPF) != 0U) { /* Waiting for the regulator to be in main mode.*/ } } else { /* Low power mode selected.*/ - while ((PWR->SR2 & PWR_SR2_REGLPF) == 0U) { /* Waiting for the regulator to be in low power mode.*/ } @@ -554,9 +552,7 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) { /* Switching to the final clock source.*/ RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & RCC_CFGR_SW_Msk); - /* Apply RCC EXTCFGR.*/ RCC->EXTCFGR = ccp->rcc_extcfgr; - while ((RCC->CFGR & RCC_CFGR_SWS) != ((ccp->rcc_cfgr & RCC_CFGR_SW_Msk) << RCC_CFGR_SWS_Pos)) { /* Waiting for clock switch.*/ } @@ -568,6 +564,7 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) { return false; } + #endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */ /*===========================================================================*/ @@ -620,13 +617,25 @@ void stm32_clock_init(void) { /* RTC clock enable.*/ #if HAL_USE_RTC - rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, false) + rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, false); #endif #if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) /* Backup domain made accessible.*/ PWR->CR1 |= PWR_CR1_DBP; + /* Static PWR initializations.*/ + PWR->CR3 = STM32_PWR_CR3; + PWR->CR4 = STM32_PWR_CR4; + PWR->PUCRA = STM32_PWR_PUCRA; + PWR->PDCRA = STM32_PWR_PDCRA; + PWR->PUCRB = STM32_PWR_PUCRB; + PWR->PDCRB = STM32_PWR_PDCRB; + PWR->PUCRC = STM32_PWR_PUCRC; + PWR->PDCRC = STM32_PWR_PDCRC; + PWR->PUCRH = STM32_PWR_PUCRH; + PWR->PDCRH = STM32_PWR_PDCRH; + /* Backup domain reset.*/ bd_reset(); @@ -635,7 +644,7 @@ void stm32_clock_init(void) { lsi_init(); /* Selecting the default clock/power/flash configuration.*/ - if (hal_lld_clock_raw_switch(&hal_clkcfg_default)) { + if (hal_lld_clock_raw_config(&hal_clkcfg_default)) { osalSysHalt("clkswc"); } @@ -656,6 +665,14 @@ void stm32_clock_init(void) { PWR->CR2 = STM32_PWR_CR2; PWR->CR3 = STM32_PWR_CR3; PWR->CR4 = STM32_PWR_CR4; + PWR->PUCRA = STM32_PWR_PUCRA; + PWR->PDCRA = STM32_PWR_PDCRA; + PWR->PUCRB = STM32_PWR_PUCRB; + PWR->PDCRB = STM32_PWR_PDCRB; + PWR->PUCRC = STM32_PWR_PUCRC; + PWR->PDCRC = STM32_PWR_PDCRC; + PWR->PUCRH = STM32_PWR_PUCRH; + PWR->PDCRH = STM32_PWR_PDCRH; /* MSI clock reset.*/ msi_reset(); @@ -724,7 +741,7 @@ bool hal_lld_clock_switch_mode(const halclkcfg_t *ccp) { return true; } - if (hal_lld_clock_raw_switch(ccp)) { + if (hal_lld_clock_raw_config(ccp)) { return true; } diff --git a/os/hal/ports/STM32/STM32WLxx/hal_lld.h b/os/hal/ports/STM32/STM32WLxx/hal_lld.h index 0b9828e31..757a5ffab 100644 --- a/os/hal/ports/STM32/STM32WLxx/hal_lld.h +++ b/os/hal/ports/STM32/STM32WLxx/hal_lld.h @@ -389,6 +389,62 @@ #define STM32_PWR_CR4 (0U) #endif +/** + * @brief PWR PUCRA register initialization value. + */ +#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRA (0U) +#endif + +/** + * @brief PWR PDCRA register initialization value. + */ +#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRA (0U) +#endif + +/** + * @brief PWR PUCRB register initialization value. + */ +#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRB (0U) +#endif + +/** + * @brief PWR PDCRB register initialization value. + */ +#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRB (0U) +#endif + +/** + * @brief PWR PUCRC register initialization value. + */ +#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRC (0U) +#endif + +/** + * @brief PWR PDCRC register initialization value. + */ +#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRC (0U) +#endif + +/** + * @brief PWR PUCRD register initialization value. + */ +#if !defined(STM32_PWR_PUCRH) || defined(__DOXYGEN__) +#define STM32_PWR_PUCRH (0U) +#endif + +/** + * @brief PWR PDCRD register initialization value. + */ +#if !defined(STM32_PWR_PDCRH) || defined(__DOXYGEN__) +#define STM32_PWR_PDCRH (0U) +#endif + /** * @brief Enables or disables the HSI16 clock source. */ @@ -1504,14 +1560,22 @@ typedef uint32_t halfreq_t; typedef struct { uint32_t pwr_cr1; uint32_t pwr_cr2; - uint32_t pwr_cr3; - uint32_t pwr_cr4; uint32_t rcc_cr; uint32_t rcc_cfgr; uint32_t rcc_extcfgr; uint32_t rcc_pllcfgr; uint32_t flash_acr; } halclkcfg_t; + +/** + * @brief Type of a clock switch-only structure. + */ +typedef struct { + uint32_t pwr_cr1; + uint32_t rcc_cfgr; + uint32_t rcc_extcfgr; + uint32_t flash_acr; +} halclkswc_t; #endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */ /*===========================================================================*/