mirror of https://github.com/rusefi/ChibiOS.git
Added GPIOv3 driver (not tested).
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8474 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
8dcb0d3dc8
commit
db45dfbe9e
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@ -16,7 +16,7 @@
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/**
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* @file STM32/GPIOv1/pal_lld.c
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* @brief STM32F1xx GPIO low level driver code.
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* @brief STM32 PAL low level driver code.
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*
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* @addtogroup PAL
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* @{
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@ -16,7 +16,7 @@
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/**
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* @file STM32/GPIOv1/pal_lld.h
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* @brief STM32F1xx GPIO low level driver header.
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* @brief STM32 PAL low level driver header.
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*
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* @addtogroup PAL
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* @{
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@ -16,7 +16,7 @@
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/**
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* @file STM32/GPIOv2/pal_lld.c
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* @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code.
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* @brief STM32 PAL low level driver code.
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*
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* @addtogroup PAL
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* @{
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@ -16,7 +16,7 @@
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/**
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* @file STM32/GPIOv2/pal_lld.h
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* @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header.
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* @brief STM32 PAL low level driver header.
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*
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* @addtogroup PAL
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* @{
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@ -0,0 +1,182 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/GPIOv3/pal_lld.c
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* @brief STM32 PAL low level driver code.
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*
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* @addtogroup PAL
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#if defined(STM32L4XX)
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#define AHB1_EN_MASK STM32_GPIO_EN_MASK
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#define AHB1_LPEN_MASK 0
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#else
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#error "missing or unsupported platform for GPIOv3 PAL driver"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) {
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gpiop->OTYPER = config->otyper;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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gpiop->AFRL = config->afrl;
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gpiop->AFRH = config->afrh;
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gpiop->MODER = config->moder;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief STM32 I/O ports configuration.
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* @details Ports A-D(E, F, G, H) clocks enabled.
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*
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* @param[in] config the STM32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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#if defined(STM32L4XX)
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RCC->AHB2ENR |= AHB1_EN_MASK;
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#endif
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/*
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* Initial GPIO setup.
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*/
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#if STM32_HAS_GPIOA
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initgpio(GPIOA, &config->PAData);
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#endif
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#if STM32_HAS_GPIOB
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initgpio(GPIOB, &config->PBData);
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#endif
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#if STM32_HAS_GPIOC
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initgpio(GPIOC, &config->PCData);
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#endif
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#if STM32_HAS_GPIOD
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initgpio(GPIOD, &config->PDData);
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#endif
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#if STM32_HAS_GPIOE
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initgpio(GPIOE, &config->PEData);
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#endif
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#if STM32_HAS_GPIOF
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initgpio(GPIOF, &config->PFData);
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#endif
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#if STM32_HAS_GPIOG
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initgpio(GPIOG, &config->PGData);
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#endif
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#if STM32_HAS_GPIOH
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initgpio(GPIOH, &config->PHData);
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#endif
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#if STM32_HAS_GPIOI
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initgpio(GPIOI, &config->PIData);
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#endif
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#if STM32_HAS_GPIOJ
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initgpio(GPIOJ, &config->PJData);
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#endif
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#if STM32_HAS_GPIOK
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initgpio(GPIOK, &config->PKData);
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
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* speed.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0;
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uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2;
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uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
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uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5;
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uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
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uint32_t ascr = (mode & PAL_STM32_ASCR_MASK) >> 11;
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uint32_t bit = 0;
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while (TRUE) {
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if ((mask & 1) != 0) {
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uint32_t altrmask, m1, m2, m4;
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altrmask = altr << ((bit & 7) * 4);
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m4 = 15 << ((bit & 7) * 4);
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if (bit < 8)
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port->AFRL = (port->AFRL & ~m4) | altrmask;
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else
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port->AFRH = (port->AFRH & ~m4) | altrmask;
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m1 = 1 << bit;
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port->OTYPER = (port->OTYPER & ~m1) | otyper;
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port->ASCR = (port->ASCR & ~m1) | ascr;
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m2 = 3 << (bit * 2);
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port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
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port->PUPDR = (port->PUPDR & ~m2) | pupdr;
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port->MODER = (port->MODER & ~m2) | moder;
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}
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mask >>= 1;
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if (!mask)
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return;
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otyper <<= 1;
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ospeedr <<= 2;
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pupdr <<= 2;
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moder <<= 2;
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bit++;
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}
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}
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#endif /* HAL_USE_PAL */
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/** @} */
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@ -0,0 +1,564 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/GPIOv3/pal_lld.h
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* @brief STM32 PAL low level driver header.
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*
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* @addtogroup PAL
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* @{
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*/
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#ifndef _PAL_LLD_H_
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#define _PAL_LLD_H_
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Unsupported modes and specific modes */
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/*===========================================================================*/
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#undef PAL_MODE_RESET
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#undef PAL_MODE_UNCONNECTED
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#undef PAL_MODE_INPUT
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#undef PAL_MODE_INPUT_PULLUP
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#undef PAL_MODE_INPUT_PULLDOWN
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#undef PAL_MODE_INPUT_ANALOG
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#undef PAL_MODE_OUTPUT_PUSHPULL
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#undef PAL_MODE_OUTPUT_OPENDRAIN
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/**
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* @name STM32-specific I/O mode flags
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* @{
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*/
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#define PAL_STM32_MODE_MASK (3U << 0U)
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#define PAL_STM32_MODE_INPUT (0U << 0U)
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#define PAL_STM32_MODE_OUTPUT (1U << 0U)
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#define PAL_STM32_MODE_ALTERNATE (2U << 0U)
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#define PAL_STM32_MODE_ANALOG (3U << 0U)
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#define PAL_STM32_OTYPE_MASK (1U << 2U)
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#define PAL_STM32_OTYPE_PUSHPULL (0U << 2U)
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#define PAL_STM32_OTYPE_OPENDRAIN (1U << 2U)
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#define PAL_STM32_OSPEED_MASK (3U << 3U)
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#define PAL_STM32_OSPEED_LOW (0U << 3U)
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#define PAL_STM32_OSPEED_MEDIUM (1U << 3U)
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#define PAL_STM32_OSPEED_FAST (2U << 3U)
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#define PAL_STM32_OSPEED_HIGH (3U << 3U)
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#define PAL_STM32_PUDR_MASK (3U << 5U)
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#define PAL_STM32_PUDR_FLOATING (0U << 5U)
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#define PAL_STM32_PUDR_PULLUP (1U << 5U)
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#define PAL_STM32_PUDR_PULLDOWN (2U << 5U)
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#define PAL_STM32_ALTERNATE_MASK (15U << 7U)
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#define PAL_STM32_ALTERNATE(n) ((n) << 7U)
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#define PAL_STM32_ASCR_MASK (1U << 11U)
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#define PAL_STM32_ASCR_OFF (0U << 11U)
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#define PAL_STM32_ASCR_ON (1U << 11U)
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/**
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* @brief Alternate function.
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*
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* @param[in] n alternate function selector
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*/
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#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \
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PAL_STM32_ALTERNATE(n))
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/** @} */
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/**
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* @name Standard I/O mode flags
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* @{
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*/
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/**
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* @brief This mode is implemented as input.
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*/
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#define PAL_MODE_RESET PAL_STM32_MODE_INPUT
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/**
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* @brief This mode is implemented as analog with analog switch disabled.
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*/
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#define PAL_MODE_UNCONNECTED (PAL_STM32_MODE_ANALOG | \
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PAL_STM32_ASCR_OFF)
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/**
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* @brief Regular input high-Z pad.
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*/
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#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT
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/**
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* @brief Input pad with weak pull up resistor.
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*/
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#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \
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PAL_STM32_PUDR_PULLUP)
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/**
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* @brief Input pad with weak pull down resistor.
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*/
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#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \
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PAL_STM32_PUDR_PULLDOWN)
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/**
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* @brief Analog input mode.
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*/
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#define PAL_MODE_INPUT_ANALOG (PAL_STM32_MODE_ANALOG | \
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PAL_STM32_ASCR_ON)
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/**
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* @brief Push-pull output pad.
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*/
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#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \
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PAL_STM32_OTYPE_PUSHPULL)
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/**
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* @brief Open-drain output pad.
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*/
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#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \
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PAL_STM32_OTYPE_OPENDRAIN)
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/** @} */
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/* Discarded definitions from the ST headers, the PAL driver uses its own
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definitions in order to have an unified handling for all devices.
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Unfortunately the ST headers have no uniform definitions for the same
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objects across the various sub-families.*/
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#undef GPIOA
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#undef GPIOB
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#undef GPIOC
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#undef GPIOD
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#undef GPIOE
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#undef GPIOF
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#undef GPIOG
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#undef GPIOH
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#undef GPIOI
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#undef GPIOJ
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#undef GPIOK
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/**
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* @name GPIO ports definitions
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* @{
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*/
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#define GPIOA ((stm32_gpio_t *)GPIOA_BASE)
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#define GPIOB ((stm32_gpio_t *)GPIOB_BASE)
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#define GPIOC ((stm32_gpio_t *)GPIOC_BASE)
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#define GPIOD ((stm32_gpio_t *)GPIOD_BASE)
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#define GPIOE ((stm32_gpio_t *)GPIOE_BASE)
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#define GPIOF ((stm32_gpio_t *)GPIOF_BASE)
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#define GPIOG ((stm32_gpio_t *)GPIOG_BASE)
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#define GPIOH ((stm32_gpio_t *)GPIOH_BASE)
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#define GPIOI ((stm32_gpio_t *)GPIOI_BASE)
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#define GPIOJ ((stm32_gpio_t *)GPIOJ_BASE)
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#define GPIOK ((stm32_gpio_t *)GPIOK_BASE)
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/** @} */
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/*===========================================================================*/
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/* I/O Ports Types and constants. */
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/*===========================================================================*/
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/**
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* @name Port related definitions
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* @{
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*/
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/**
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* @brief Width, in bits, of an I/O port.
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*/
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#define PAL_IOPORTS_WIDTH 16
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/**
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* @brief Whole port mask.
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* @details This macro specifies all the valid bits into a port.
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*/
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#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
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/** @} */
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/**
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* @name Line handling macros
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* @{
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*/
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/**
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* @brief Forms a line identifier.
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* @details A port/pad pair are encoded into an @p ioline_t type. The encoding
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* of this type is platform-dependent.
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* @note In this driver the pad number is encoded in the lower 4 bits of
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* the GPIO address which are guaranteed to be zero.
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*/
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#define PAL_LINE(port, pad) \
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((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
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/**
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* @brief Decodes a port identifier from a line identifier.
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*/
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#define PAL_PORT(line) \
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((stm32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
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/**
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* @brief Decodes a pad identifier from a line identifier.
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*/
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#define PAL_PAD(line) \
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((uint32_t)((uint32_t)(line) & 0x0000000FU))
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/**
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* @brief Value identifying an invalid line.
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*/
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#define PAL_NOLINE 0U
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/** @} */
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/**
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* @brief STM32 GPIO registers block.
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*/
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typedef struct {
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volatile uint32_t MODER;
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volatile uint32_t OTYPER;
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volatile uint32_t OSPEEDR;
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volatile uint32_t PUPDR;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile union {
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uint32_t W;
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struct {
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uint16_t set;
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uint16_t clear;
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} H;
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} BSRR;
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volatile uint32_t LCKR;
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volatile uint32_t AFRL;
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volatile uint32_t AFRH;
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volatile uint32_t BRR;
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volatile uint32_t ASCR;
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} stm32_gpio_t;
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/**
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* @brief GPIO port setup info.
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*/
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typedef struct {
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/** Initial value for MODER register.*/
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uint32_t moder;
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/** Initial value for OTYPER register.*/
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uint32_t otyper;
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/** Initial value for OSPEEDR register.*/
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uint32_t ospeedr;
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/** Initial value for PUPDR register.*/
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uint32_t pupdr;
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/** Initial value for ODR register.*/
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uint32_t odr;
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/** Initial value for AFRL register.*/
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uint32_t afrl;
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/** Initial value for AFRH register.*/
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||||
uint32_t afrh;
|
||||
/** Initial value for ASCR register.*/
|
||||
uint32_t ascr;
|
||||
} stm32_gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 GPIO static initializer.
|
||||
* @details An instance of this structure must be passed to @p palInit() at
|
||||
* system startup time in order to initialize the digital I/O
|
||||
* subsystem. This represents only the initial setup, specific pads
|
||||
* or whole ports can be reprogrammed at later time.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
/** @brief Port A setup data.*/
|
||||
stm32_gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
/** @brief Port B setup data.*/
|
||||
stm32_gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
/** @brief Port C setup data.*/
|
||||
stm32_gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
/** @brief Port D setup data.*/
|
||||
stm32_gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
/** @brief Port E setup data.*/
|
||||
stm32_gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
/** @brief Port F setup data.*/
|
||||
stm32_gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
/** @brief Port G setup data.*/
|
||||
stm32_gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
/** @brief Port H setup data.*/
|
||||
stm32_gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
/** @brief Port I setup data.*/
|
||||
stm32_gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
/** @brief Port I setup data.*/
|
||||
stm32_gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
/** @brief Port I setup data.*/
|
||||
stm32_gpio_setup_t PKData;
|
||||
#endif
|
||||
} PALConfig;
|
||||
|
||||
/**
|
||||
* @brief Type of digital I/O port sized unsigned integer.
|
||||
*/
|
||||
typedef uint32_t ioportmask_t;
|
||||
|
||||
/**
|
||||
* @brief Type of digital I/O modes.
|
||||
*/
|
||||
typedef uint32_t iomode_t;
|
||||
|
||||
/**
|
||||
* @brief Type of an I/O line.
|
||||
*/
|
||||
typedef uint32_t ioline_t;
|
||||
|
||||
/**
|
||||
* @brief Port Identifier.
|
||||
* @details This type can be a scalar or some kind of pointer, do not make
|
||||
* any assumption about it, use the provided macros when populating
|
||||
* variables of this type.
|
||||
*/
|
||||
typedef stm32_gpio_t * ioportid_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I/O Ports Identifiers. */
|
||||
/* The low level driver wraps the definitions already present in the STM32 */
|
||||
/* firmware library. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO port A identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
#define IOPORT1 GPIOA
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port B identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
#define IOPORT2 GPIOB
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port C identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
#define IOPORT3 GPIOC
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port D identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
#define IOPORT4 GPIOD
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port E identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
#define IOPORT5 GPIOE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port F identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
#define IOPORT6 GPIOF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port G identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
#define IOPORT7 GPIOG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port H identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
#define IOPORT8 GPIOH
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port I identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
#define IOPORT9 GPIOI
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port J identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
#define IOPORT10 GPIOJ
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port K identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
#define IOPORT11 GPIOK
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Implementation, some of the following macros could be implemented as */
|
||||
/* functions, if so please put them in pal_lld.c. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO ports subsystem initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_init(config) _pal_lld_init(config)
|
||||
|
||||
/**
|
||||
* @brief Reads an I/O port.
|
||||
* @details This function is implemented by reading the GPIO IDR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The port bits.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readport(port) ((port)->IDR)
|
||||
|
||||
/**
|
||||
* @brief Reads the output latch.
|
||||
* @details This function is implemented by reading the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The latched logical states.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readlatch(port) ((port)->ODR)
|
||||
|
||||
/**
|
||||
* @brief Writes on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be written on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Sets a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be ORed on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
|
||||
|
||||
/**
|
||||
* @brief Clears a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be cleared on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
|
||||
|
||||
/**
|
||||
* @brief Writes a group of bits.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset the group bit offset within the port
|
||||
* @param[in] bits bits to be written. Values exceeding the group
|
||||
* width are masked.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writegroup(port, mask, offset, bits) \
|
||||
((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \
|
||||
(((bits) & (mask)) << (offset)))
|
||||
|
||||
/**
|
||||
* @brief Pads group mode setup.
|
||||
* @details This function programs a pads group belonging to the same port
|
||||
* with the specified mode.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset group bit offset within the port
|
||||
* @param[in] mode group mode
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setgroupmode(port, mask, offset, mode) \
|
||||
_pal_lld_setgroupmode(port, mask << offset, mode)
|
||||
|
||||
/**
|
||||
* @brief Writes a logical state on an output pad.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] pad pad number within the port
|
||||
* @param[in] bit logical value, the value must be @p PAL_LOW or
|
||||
* @p PAL_HIGH
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
|
||||
|
||||
extern const PALConfig pal_default_config;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void _pal_lld_init(const PALConfig *config);
|
||||
void _pal_lld_setgroupmode(ioportid_t port,
|
||||
ioportmask_t mask,
|
||||
iomode_t mode);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_PAL */
|
||||
|
||||
#endif /* _PAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -20,7 +20,7 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \
|
|||
$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c
|
||||
|
|
@ -58,7 +58,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
|||
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
|
||||
|
|
@ -79,7 +79,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
|||
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2 \
|
||||
|
|
|
|||
|
|
@ -157,14 +157,14 @@
|
|||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_HAS_GPIOJ FALSE
|
||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
|
||||
RCC_IOPENR_GPIOBEN | \
|
||||
RCC_IOPENR_GPIOCEN | \
|
||||
RCC_IOPENR_GPIODEN | \
|
||||
RCC_IOPENR_GPIOEEN | \
|
||||
RCC_IOPENR_GPIOFEN | \
|
||||
RCC_IOPENR_GPIOGEN | \
|
||||
RCC_IOPENR_GPIOHEN)
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
|
||||
RCC_AHB2ENR_GPIOBEN | \
|
||||
RCC_AHB2ENR_GPIOCEN | \
|
||||
RCC_AHB2ENR_GPIODEN | \
|
||||
RCC_AHB2ENR_GPIOEEN | \
|
||||
RCC_AHB2ENR_GPIOFEN | \
|
||||
RCC_AHB2ENR_GPIOGEN | \
|
||||
RCC_AHB2ENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
|
|
|
|||
|
|
@ -73,6 +73,10 @@
|
|||
*****************************************************************************
|
||||
|
||||
*** 3.1.0 ***
|
||||
- HAL: Introduced preliminary support for STM32F7xx devices.
|
||||
- HAL: Introduced preliminary support for STM32L4xx devices.
|
||||
- HAL: Introduced preliminary support for STM32L0xx devices.
|
||||
- HAL: Added PAL driver for STM32L4xx GPIOv3 peripheral.
|
||||
- HAL: Added I2S driver for STM32 SPIv2 peripheral.
|
||||
- HAL: Added demos and board files for ST's Nucleo32 boards (F031, F042, F303).
|
||||
- HAL: Added "lines" handling to PAL driver, lines are identifiers of both
|
||||
|
|
@ -119,8 +123,6 @@
|
|||
- HAL: STM32F0xx and STM32L0xx devices now share the same ADCv1 driver.
|
||||
- HAL: STM32F0xx, STM32F1xx, STM32F3xx, STM32F37x, STM32L0xx and STM32L1xx
|
||||
devices now share the same DMAv1 driver.
|
||||
- HAL: Introduced preliminary support for STM32F7xx devices.
|
||||
- HAL: Introduced preliminary support for STM32L0xx devices.
|
||||
- HAL: New STM32 shared DMAv2 driver supporting channel selection and
|
||||
data cache invalidation (F2, F4, F7).
|
||||
- HAL: New STM32 shared DMAv1 driver supporting channel selection and fixing
|
||||
|
|
|
|||
Loading…
Reference in New Issue