mirror of https://github.com/rusefi/ChibiOS.git
I2C. Added support of stm32f1x.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3557 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -46,28 +46,28 @@
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/**
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/**
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* @brief I2C1 driver enable switch.
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* @brief I2C1 driver enable switch.
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* @details If set to @p TRUE the support for I2C1 is included.
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* @details If set to @p TRUE the support for I2C1 is included.
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* @note The default is @p TRUE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
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#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C1 TRUE
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#define STM32_I2C_USE_I2C1 FALSE
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#endif
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#endif
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/**
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/**
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* @brief I2C2 driver enable switch.
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* @brief I2C2 driver enable switch.
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* @details If set to @p TRUE the support for I2C2 is included.
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* @details If set to @p TRUE the support for I2C2 is included.
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* @note The default is @p TRUE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
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#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C2 TRUE
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#define STM32_I2C_USE_I2C2 FALSE
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#endif
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#endif
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/**
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/**
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* @brief I2C3 driver enable switch.
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* @brief I2C3 driver enable switch.
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* @details If set to @p TRUE the support for I2C3 is included.
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* @details If set to @p TRUE the support for I2C3 is included.
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* @note The default is @p TRUE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
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#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C3 TRUE
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#define STM32_I2C_USE_I2C3 FALSE
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#endif
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#endif
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/**
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/**
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@ -93,13 +93,83 @@
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#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_IRQ_PRIORITY 0xA0
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#define STM32_I2C_I2C3_IRQ_PRIORITY 0xA0
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#endif
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#endif
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/**
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* @brief I2C1 DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* error can only happen because programming errors.
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*/
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#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_I2C_DMA_ERROR_HOOK(uartp) chSysHalt()
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#endif
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#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
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/**
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* @brief DMA stream used for I2C1 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#endif
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/**
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* @brief DMA stream used for I2C1 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#endif
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/**
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* @brief DMA stream used for I2C2 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#endif
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/**
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* @brief DMA stream used for I2C2 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#endif
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/**
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* @brief DMA stream used for I2C3 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#endif
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/**
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* @brief DMA stream used for I2C3 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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#else /* !STM32_ADVANCED_DMA */
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/* Fixed streams for platforms using the old DMA peripheral, the values are
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valid for both STM32F1xx and STM32L1xx.*/
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif /* !STM32_ADVANCED_DMA*/
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/** @} */
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/** @} */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/** @brief EV5 */
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/** @brief flags for interrupt handling */
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#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) /* BUSY, MSL and SB flag */
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#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) /* BUSY, MSL and SB flag */
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | I2C_SR1_BTF | I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | I2C_SR1_BTF | I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */
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#define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */
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#define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */
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@ -107,6 +177,94 @@
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#define I2C_FLG_MASTER_RECEIVER 0x10
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#define I2C_FLG_MASTER_RECEIVER 0x10
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#define I2C_FLG_HEADER_SENT 0x80
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#define I2C_FLG_HEADER_SENT 0x80
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#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
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#error "I2C1 not present in the selected device"
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#endif
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#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
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#error "I2C2 not present in the selected device"
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#endif
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#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3
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#error "I2C3 not present in the selected device"
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#endif
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#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \
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!STM32_I2C_USE_I2C3
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#error "I2C driver activated but no I2C peripheral assigned"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART1 RX"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART1 TX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART2 RX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART2 TX"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \
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STM32_I2C3_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART3 RX"
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#endif
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#if STM32_I2C_USE_I2C3 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \
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STM32_I2C3_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART3 TX"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/* Driver data structures and types. */
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/* I2C attributes.*/
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_RTC TRUE
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