From e1fbdd2cd6e0614aeb14387c4e0922e5bd64503a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Aug 2013 09:25:18 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6129 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/TIMv1/stm32_tim.h | 438 +++++++++++++++++++++++ os/hal/platforms/STM32/icu_lld.c | 56 +-- os/hal/platforms/STM32/icu_lld.h | 2 + os/hal/platforms/STM32/pwm_lld.c | 86 +++-- os/hal/platforms/STM32/pwm_lld.h | 2 + os/hal/platforms/STM32/stm32.h | 62 ---- 6 files changed, 512 insertions(+), 134 deletions(-) create mode 100644 os/hal/platforms/STM32/TIMv1/stm32_tim.h diff --git a/os/hal/platforms/STM32/TIMv1/stm32_tim.h b/os/hal/platforms/STM32/TIMv1/stm32_tim.h new file mode 100644 index 000000000..1db882ebc --- /dev/null +++ b/os/hal/platforms/STM32/TIMv1/stm32_tim.h @@ -0,0 +1,438 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file stm32_timh + * @brief STM32 TIM registers layout header. + * @note This file requires definitions from the ST STM32 header file. + * + * @addtogroup STM32_TIM + * @{ + */ + +#ifndef _STM32_TIM_H_ +#define _STM32_TIM_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name TIM_CR1 register + * @{ + */ +#define STM32_TIM_CR1_CEN (1U << 0) +#define STM32_TIM_CR1_UDIS (1U << 1) +#define STM32_TIM_CR1_URS (1U << 2) +#define STM32_TIM_CR1_OPM (1U << 3) +#define STM32_TIM_CR1_DIR (1U << 4) + +#define STM32_TIM_CR1_CMS_MASK (3U << 4) +#define STM32_TIM_CR1_CMS(n) ((n) << 5) + +#define STM32_TIM_CR1_ARPE (1U << 7) + +#define STM32_TIM_CR1_CKD_MASK (3U << 8) +#define STM32_TIM_CR1_CKD(n) ((n) << 8) + +#define STM32_TIM_CR1_UIFREMAP (1U << 11) +/** @} */ + +/** + * @name TIM_CR2 register + * @{ + */ +#define STM32_TIM_CR2_CCPC (1U << 0) +#define STM32_TIM_CR2_CCUS (1U << 2) +#define STM32_TIM_CR2_CCDS (1U << 3) + +#define STM32_TIM_CR2_MMS_MASK (7U << 4) +#define STM32_TIM_CR2_MMS(n) ((n) << 4) + +#define STM32_TIM_CR2_TI1S (1U << 7) +#define STM32_TIM_CR2_OIS1 (1U << 8) +#define STM32_TIM_CR2_OIS1N (1U << 9) +#define STM32_TIM_CR2_OIS2 (1U << 10) +#define STM32_TIM_CR2_OIS2N (1U << 11) +#define STM32_TIM_CR2_OIS3 (1U << 12) +#define STM32_TIM_CR2_OIS3N (1U << 13) +#define STM32_TIM_CR2_OIS4 (1U << 14) +#define STM32_TIM_CR2_OIS5 (1U << 16) +#define STM32_TIM_CR2_OIS6 (1U << 17) + +#define STM32_TIM_CR2_MMS2_MASK (15U << 20) +#define STM32_TIM_CR2_MMS2(n) ((n) << 20) +/** @} */ + +/** + * @name TIM_SMCR register + * @{ + */ +#define STM32_TIM_SMCR_SMS_MASK 0x00010007 +#define STM32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) | \ + (((n) & 8) << 16)) + +#define STM32_TIM_SMCR_OCCS (1U << 3) + +#define STM32_TIM_SMCR_TS_MASK (7U << 4) +#define STM32_TIM_SMCR_TS(n) ((n) << 4) + +#define STM32_TIM_SMCR_MSM (1U << 7) + +#define STM32_TIM_SMCR_ETF_MASK (15U << 8) +#define STM32_TIM_SMCR_ETF(n) ((n) << 8) + +#define STM32_TIM_SMCR_ETPS_MASK (3U << 12) +#define STM32_TIM_SMCR_ETPS(n) ((n) << 12) + +#define STM32_TIM_SMCR_ECE (1U << 14) +#define STM32_TIM_SMCR_ETP (1U << 15) +/** @} */ + +/** + * @name TIM_DIER register + * @{ + */ +#define STM32_TIM_DIER_UIE (1U << 0) +#define STM32_TIM_DIER_CC1IE (1U << 1) +#define STM32_TIM_DIER_CC2IE (1U << 2) +#define STM32_TIM_DIER_CC3IE (1U << 3) +#define STM32_TIM_DIER_CC4IE (1U << 4) +#define STM32_TIM_DIER_COMIE (1U << 5) +#define STM32_TIM_DIER_TIE (1U << 6) +#define STM32_TIM_DIER_BIE (1U << 7) +#define STM32_TIM_DIER_UDE (1U << 8) +#define STM32_TIM_DIER_CC1DE (1U << 9) +#define STM32_TIM_DIER_CC2DE (1U << 10) +#define STM32_TIM_DIER_CC3DE (1U << 11) +#define STM32_TIM_DIER_CC4DE (1U << 12) +#define STM32_TIM_DIER_COMDE (1U << 13) +#define STM32_TIM_DIER_TDE (1U << 14) +/** @} */ + +/** + * @name TIM_SR register + * @{ + */ +#define STM32_TIM_SR_UIF (1U << 0) +#define STM32_TIM_SR_CC1IF (1U << 1) +#define STM32_TIM_SR_CC2IF (1U << 2) +#define STM32_TIM_SR_CC3IF (1U << 3) +#define STM32_TIM_SR_CC4IF (1U << 4) +#define STM32_TIM_SR_COMIF (1U << 5) +#define STM32_TIM_SR_TIF (1U << 6) +#define STM32_TIM_SR_BIF (1U << 7) +#define STM32_TIM_SR_B2IF (1U << 8) +#define STM32_TIM_SR_CC1OF (1U << 9) +#define STM32_TIM_SR_CC2OF (1U << 10) +#define STM32_TIM_SR_CC3OF (1U << 11) +#define STM32_TIM_SR_CC4OF (1U << 12) +#define STM32_TIM_SR_CC5IF (1U << 16) +#define STM32_TIM_SR_CC6IF (1U << 17) +/** @} */ + +/** + * @name TIM_EGR register + * @{ + */ +#define STM32_TIM_EGR_UG (1U << 0) +#define STM32_TIM_EGR_CC1G (1U << 1) +#define STM32_TIM_EGR_CC2G (1U << 2) +#define STM32_TIM_EGR_CC3G (1U << 3) +#define STM32_TIM_EGR_CC4G (1U << 4) +#define STM32_TIM_EGR_COMG (1U << 5) +#define STM32_TIM_EGR_TG (1U << 6) +#define STM32_TIM_EGR_BG (1U << 7) +#define STM32_TIM_EGR_B2G (1U << 8) +/** @} */ + +/** + * @name TIM_CCMR1 register (output) + * @{ + */ +#define STM32_TIM_CCMR1_CC1S_MASK (3U << 0) +#define STM32_TIM_CCMR1_CC1S(n) ((n) << 0) + +#define STM32_TIM_CCMR1_OC1FE (1U << 2) +#define STM32_TIM_CCMR1_OC1PE (1U << 3) + +#define STM32_TIM_CCMR1_OC1M_MASK 0x00010070 +#define STM32_TIM_CCMR1_OC1M(n) ((((n) & 3) << 4) | \ + (((n) & 4) << 16)) + +#define STM32_TIM_CCMR1_OC1CE (1U << 7) + +#define STM32_TIM_CCMR1_CC2S_MASK (3U << 8) +#define STM32_TIM_CCMR1_CC2S(n) ((n) << 8) + +#define STM32_TIM_CCMR1_OC2FE (1U << 10) +#define STM32_TIM_CCMR1_OC2PE (1U << 11) + +#define STM32_TIM_CCMR1_OC2M_MASK 0x01007000 +#define STM32_TIM_CCMR1_OC2M(n) ((((n) & 3) << 8) | \ + (((n) & 4) << 24)) + +#define STM32_TIM_CCMR1_OC2CE (1U << 15) +/** @} */ + +/** + * @name CCMR1 register (input) + * @{ + */ +#define STM32_TIM_CCMR1_IC1PSC_MASK (3U << 2) +#define STM32_TIM_CCMR1_IC1PSC(n) ((n) << 2) + +#define STM32_TIM_CCMR1_IC1F_MASK (15U << 4) +#define STM32_TIM_CCMR1_IC1F(n) ((n) << 4) + +#define STM32_TIM_CCMR1_IC2PSC_MASK (3U << 10) +#define STM32_TIM_CCMR1_IC2PSC(n) ((n) << 10) + +#define STM32_TIM_CCMR1_IC2F_MASK (15U << 12) +#define STM32_TIM_CCMR1_IC2F(n) ((n) << 12) +/** @} */ + +/** + * @name TIM_CCMR2 register (output) + * @{ + */ +#define STM32_TIM_CCMR2_CC3S_MASK (3U << 0) +#define STM32_TIM_CCMR2_CC3S(n) ((n) << 0) + +#define STM32_TIM_CCMR2_OC3FE (1U << 2) +#define STM32_TIM_CCMR2_OC3PE (1U << 3) + +#define STM32_TIM_CCMR2_OC3M_MASK 0x00010070 +#define STM32_TIM_CCMR2_OC3M(n) ((((n) & 3) << 4) | \ + (((n) & 4) << 16)) + +#define STM32_TIM_CCMR2_OC3CE (1U << 7) + +#define STM32_TIM_CCMR2_CC4S_MASK (3U << 8) +#define STM32_TIM_CCMR2_CC4S(n) ((n) << 8) + +#define STM32_TIM_CCMR2_OC4FE (1U << 10) +#define STM32_TIM_CCMR2_OC4PE (1U << 11) + +#define STM32_TIM_CCMR2_OC4M_MASK 0x01007000 +#define STM32_TIM_CCMR2_OC4M(n) ((((n) & 3) << 8) | \ + (((n) & 4) << 24)) + +#define STM32_TIM_CCMR2_OC4CE (1U << 15) +/** @} */ + +/** + * @name TIM_CCMR2 register (input) + * @{ + */ +#define STM32_TIM_CCMR2_IC3PSC_MASK (3U << 2) +#define STM32_TIM_CCMR2_IC3PSC(n) ((n) << 2) + +#define STM32_TIM_CCMR2_IC3F_MASK (15U << 4) +#define STM32_TIM_CCMR2_IC3F(n) ((n) << 4) + +#define STM32_TIM_CCMR2_IC4PSC_MASK (3U << 10) +#define STM32_TIM_CCMR2_IC4PSC(n) ((n) << 10) + +#define STM32_TIM_CCMR2_IC4F_MASK (15U << 12) +#define STM32_TIM_CCMR2_IC4F(n) ((n) << 12) +/** @} */ + +/** + * @name TIM_CCER register + * @{ + */ +#define STM32_TIM_CCER_CC1E (1U << 0) +#define STM32_TIM_CCER_CC1P (1U << 1) +#define STM32_TIM_CCER_CC1NE (1U << 2) +#define STM32_TIM_CCER_CC1NP (1U << 3) +#define STM32_TIM_CCER_CC2E (1U << 4) +#define STM32_TIM_CCER_CC2P (1U << 5) +#define STM32_TIM_CCER_CC2NE (1U << 6) +#define STM32_TIM_CCER_CC2NP (1U << 7) +#define STM32_TIM_CCER_CC3E (1U << 8) +#define STM32_TIM_CCER_CC3P (1U << 9) +#define STM32_TIM_CCER_CC3NE (1U << 10) +#define STM32_TIM_CCER_CC3NP (1U << 11) +#define STM32_TIM_CCER_CC4E (1U << 12) +#define STM32_TIM_CCER_CC4P (1U << 13) +#define STM32_TIM_CCER_CC4NP (1U << 15) +#define STM32_TIM_CCER_CC5E (1U << 16) +#define STM32_TIM_CCER_CC5P (1U << 17) +#define STM32_TIM_CCER_CC6E (1U << 20) +#define STM32_TIM_CCER_CC6P (1U << 21) +/** @} */ + +/** + * @name TIM_CNT register + * @{ + */ +#define STM32_TIM_CNT_UIFCPY (1U << 31) +/** @} */ + +/** + * @name TIM_BDTR register + * @{ + */ +#define STM32_TIM_BDTR_DTG_MASK (255U << 0) +#define STM32_TIM_BDTR_DTG(n) ((n) << 0) + +#define STM32_TIM_BDTR_LOCK_MASK (3U << 8) +#define STM32_TIM_BDTR_LOCK(n) ((n) << 8) + +#define STM32_TIM_BDTR_OSSI (1U << 10) +#define STM32_TIM_BDTR_OSSR (1U << 11) +#define STM32_TIM_BDTR_BKE (1U << 12) +#define STM32_TIM_BDTR_BKP (1U << 13) +#define STM32_TIM_BDTR_AOE (1U << 14) +#define STM32_TIM_BDTR_MOE (1U << 15) + +#define STM32_TIM_BDTR_BKF_MASK (15U << 16) +#define STM32_TIM_BDTR_BKF(n) ((n) << 16) +#define STM32_TIM_BDTR_BK2F_MASK (15U << 20) +#define STM32_TIM_BDTR_BK2F(n) ((n) << 20) + +#define STM32_TIM_BDTR_BK2E (1U << 24) +#define STM32_TIM_BDTR_BK2P (1U << 25) +/** @} */ + +/** + * @name TIM_DCR register + * @{ + */ +#define STM32_TIM_DCR_DBA_MASK (31U << 0) +#define STM32_TIM_DCR_DBA(n) ((n) << 0) + +#define STM32_TIM_DCR_DBL_MASK (31U << 8) +#define STM32_TIM_DCR_DBL(b) ((n) << 8) +/** @} */ + +/** + * @name TIM16_OR register + * @{ + */ +#define STM32_TIM16_OR_TI1_RMP_MASK (3U << 6) +#define STM32_TIM16_OR_TI1_RMP(n) ((n) << 6) +/** @} */ + +/** + * @name TIM_OR register + * @{ + */ +#define STM32_TIM_OR_ETR_RMP_MASK (15U << 0) +#define STM32_TIM_OR_ETR_RMP(n) ((n) << 0) +/** @} */ + +/** + * @name TIM_CCMR3 register + * @{ + */ +#define STM32_TIM_CCMR3_OC5FE (1U << 2) +#define STM32_TIM_CCMR3_OC5PE (1U << 3) + +#define STM32_TIM_CCMR3_OC5M_MASK 0x00010070 +#define STM32_TIM_CCMR3_OC5M(n) ((((n) & 3) << 4) | \ + (((n) & 4) << 16)) + +#define STM32_TIM_CCMR3_OC5CE (1U << 7) + +#define STM32_TIM_CCMR3_OC6FE (1U << 10) +#define STM32_TIM_CCMR3_OC6PE (1U << 11) + +#define STM32_TIM_CCMR3_OC6M_MASK 0x01007000 +#define STM32_TIM_CCMR3_OC6M(n) ((((n) & 3) << 8) | \ + (((n) & 4) << 24)) + +#define STM32_TIM_CCMR3_OC6CE (1U << 15) +/** @} */ + +/** + * @name TIM units references + * @{ + */ +#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) +#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) +#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) +#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) +#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) +#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) +#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) +#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) +#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) +#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) +#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) +#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) +#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) +#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) +#define STM32_TIM15 ((stm32_tim_t *)TIM15_BASE) +#define STM32_TIM16 ((stm32_tim_t *)TIM16_BASE) +#define STM32_TIM17 ((stm32_tim_t *)TIM17_BASE) +#define STM32_TIM18 ((stm32_tim_t *)TIM18_BASE) +#define STM32_TIM19 ((stm32_tim_t *)TIM19_BASE) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 TIM registers block. + * @note This is the most general known form, not all timers have + * necessarily all registers and bits. + */ +typedef struct { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMCR; + volatile uint32_t DIER; + volatile uint32_t SR; + volatile uint32_t EGR; + volatile uint32_t CCMR1; + volatile uint32_t CCMR2; + volatile uint32_t CCER; + volatile uint32_t CNT; + volatile uint32_t PSC; + volatile uint32_t ARR; + volatile uint32_t RCR; + volatile uint32_t CCR[4]; + volatile uint32_t BDTR; + volatile uint32_t DCR; + volatile uint32_t DMAR; + volatile uint32_t OR; + volatile uint32_t CCMR3; + volatile uint32_t CCR5; + volatile uint32_t CCR6; +} stm32_tim_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_TIM_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index 2e3c4334b..ad838d903 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -115,17 +115,17 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) { sr &= icup->tim->DIER; icup->tim->SR = ~sr; if (icup->config->channel == ICU_CHANNEL_1) { - if ((sr & TIM_SR_CC1IF) != 0) + if ((sr & STM32_TIM_SR_CC1IF) != 0) _icu_isr_invoke_period_cb(icup); - if ((sr & TIM_SR_CC2IF) != 0) + if ((sr & STM32_TIM_SR_CC2IF) != 0) _icu_isr_invoke_width_cb(icup); } else { - if ((sr & TIM_SR_CC1IF) != 0) + if ((sr & STM32_TIM_SR_CC1IF) != 0) _icu_isr_invoke_width_cb(icup); - if ((sr & TIM_SR_CC2IF) != 0) + if ((sr & STM32_TIM_SR_CC2IF) != 0) _icu_isr_invoke_period_cb(icup); } - if ((sr & TIM_SR_UIF) != 0) + if ((sr & STM32_TIM_SR_UIF) != 0) _icu_isr_invoke_overflow_cb(icup); } @@ -487,21 +487,22 @@ void icu_lld_start(ICUDriver *icup) { /* Selected input 1. CCMR1_CC1S = 01 = CH1 Input on TI1. CCMR1_CC2S = 10 = CH2 Input on TI1.*/ - icup->tim->CCMR1 = TIM_CCMR1_CC1S_0 | - TIM_CCMR1_CC2S_1; + icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(1) | STM32_TIM_CCMR1_CC2S(2); + /* SMCR_TS = 101, input is TI1FP1. SMCR_SMS = 100, reset on rising edge.*/ - icup->tim->SMCR = TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | - TIM_SMCR_SMS_2; + icup->tim->SMCR = STM32_TIM_SMCR_TS(5) | STM32_TIM_SMCR_SMS(4); + /* The CCER settings depend on the selected trigger mode. ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) - icup->tim->CCER = TIM_CCER_CC1E | - TIM_CCER_CC2E | TIM_CCER_CC2P; + icup->tim->CCER = STM32_TIM_CCER_CC1E | + STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; else - icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | - TIM_CCER_CC2E; + icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | + STM32_TIM_CCER_CC2E; + /* Direct pointers to the capture registers in order to make reading data faster from within callbacks.*/ icup->wccrp = &icup->tim->CCR[1]; @@ -510,21 +511,22 @@ void icu_lld_start(ICUDriver *icup) { /* Selected input 2. CCMR1_CC1S = 10 = CH1 Input on TI2. CCMR1_CC2S = 01 = CH2 Input on TI2.*/ - icup->tim->CCMR1 = TIM_CCMR1_CC1S_1 | - TIM_CCMR1_CC2S_0; + icup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(2) | STM32_TIM_CCMR1_CC2S(1); + /* SMCR_TS = 110, input is TI2FP2. SMCR_SMS = 100, reset on rising edge.*/ - icup->tim->SMCR = TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | - TIM_SMCR_SMS_2; + icup->tim->SMCR = STM32_TIM_SMCR_TS(6) | STM32_TIM_SMCR_SMS(4); + /* The CCER settings depend on the selected trigger mode. ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. ICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) - icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | - TIM_CCER_CC2E; + icup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | + STM32_TIM_CCER_CC2E; else - icup->tim->CCER = TIM_CCER_CC1E | - TIM_CCER_CC2E | TIM_CCER_CC2P; + icup->tim->CCER = STM32_TIM_CCER_CC1E | + STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; + /* Direct pointers to the capture registers in order to make reading data faster from within callbacks.*/ icup->wccrp = &icup->tim->CCR[0]; @@ -606,18 +608,18 @@ void icu_lld_enable(ICUDriver *icup) { icup->tim->SR = 0; /* Clear pending IRQs (if any). */ if (icup->config->channel == ICU_CHANNEL_1) { if (icup->config->period_cb != NULL) - icup->tim->DIER |= TIM_DIER_CC1IE; + icup->tim->DIER |= STM32_TIM_DIER_CC1IE; if (icup->config->width_cb != NULL) - icup->tim->DIER |= TIM_DIER_CC2IE; + icup->tim->DIER |= STM32_TIM_DIER_CC2IE; } else { if (icup->config->width_cb != NULL) - icup->tim->DIER |= TIM_DIER_CC1IE; + icup->tim->DIER |= STM32_TIM_DIER_CC1IE; if (icup->config->period_cb != NULL) - icup->tim->DIER |= TIM_DIER_CC2IE; + icup->tim->DIER |= STM32_TIM_DIER_CC2IE; } if (icup->config->overflow_cb != NULL) - icup->tim->DIER |= TIM_DIER_UIE; - icup->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; + icup->tim->DIER |= STM32_TIM_DIER_UIE; + icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; } /** diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index ee5f313f3..ad6ddffe5 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -25,6 +25,8 @@ #ifndef _ICU_LLD_H_ #define _ICU_LLD_H_ +#include "stm32_tim.h" + #if HAL_USE_ICU || defined(__DOXYGEN__) /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index eb44d308a..97114ac79 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -115,15 +115,15 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { sr = pwmp->tim->SR; sr &= pwmp->tim->DIER; pwmp->tim->SR = ~sr; - if ((sr & TIM_SR_CC1IF) != 0) + if ((sr & STM32_TIM_SR_CC1IF) != 0) pwmp->config->channels[0].callback(pwmp); - if ((sr & TIM_SR_CC2IF) != 0) + if ((sr & STM32_TIM_SR_CC2IF) != 0) pwmp->config->channels[1].callback(pwmp); - if ((sr & TIM_SR_CC3IF) != 0) + if ((sr & STM32_TIM_SR_CC3IF) != 0) pwmp->config->channels[2].callback(pwmp); - if ((sr & TIM_SR_CC4IF) != 0) + if ((sr & STM32_TIM_SR_CC4IF) != 0) pwmp->config->channels[3].callback(pwmp); - if ((sr & TIM_SR_UIF) != 0) + if ((sr & STM32_TIM_SR_UIF) != 0) pwmp->config->callback(pwmp); } #endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */ @@ -148,7 +148,7 @@ CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { CH_IRQ_PROLOGUE(); - STM32_TIM1->SR = ~TIM_SR_UIF; + STM32_TIM1->SR = ~STM32_TIM_SR_UIF; PWMD1.config->callback(&PWMD1); CH_IRQ_EPILOGUE(); @@ -171,15 +171,15 @@ CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { CH_IRQ_PROLOGUE(); sr = STM32_TIM1->SR & STM32_TIM1->DIER; - STM32_TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | - TIM_SR_CC3IF | TIM_SR_CC4IF); - if ((sr & TIM_SR_CC1IF) != 0) + STM32_TIM1->SR = ~(STM32_TIM_SR_CC1IF | STM32_TIM_SR_CC2IF | + STM32_TIM_SR_CC3IF | STM32_TIM_SR_CC4IF); + if ((sr & STM32_TIM_SR_CC1IF) != 0) PWMD1.config->channels[0].callback(&PWMD1); - if ((sr & TIM_SR_CC2IF) != 0) + if ((sr & STM32_TIM_SR_CC2IF) != 0) PWMD1.config->channels[1].callback(&PWMD1); - if ((sr & TIM_SR_CC3IF) != 0) + if ((sr & STM32_TIM_SR_CC3IF) != 0) PWMD1.config->channels[2].callback(&PWMD1); - if ((sr & TIM_SR_CC4IF) != 0) + if ((sr & STM32_TIM_SR_CC4IF) != 0) PWMD1.config->channels[3].callback(&PWMD1); CH_IRQ_EPILOGUE(); @@ -301,15 +301,15 @@ CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { CH_IRQ_PROLOGUE(); sr = STM32_TIM8->SR & STM32_TIM8->DIER; - STM32_TIM8->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | - TIM_SR_CC3IF | TIM_SR_CC4IF); - if ((sr & TIM_SR_CC1IF) != 0) + STM32_TIM8->SR = ~(STM32_TIM_SR_CC1IF | STM32_TIM_SR_CC2IF | + STM32_TIM_SR_CC3IF | STM32_TIM_SR_CC4IF); + if ((sr & STM32_TIM_SR_CC1IF) != 0) PWMD8.config->channels[0].callback(&PWMD8); - if ((sr & TIM_SR_CC2IF) != 0) + if ((sr & STM32_TIM_SR_CC2IF) != 0) PWMD8.config->channels[1].callback(&PWMD8); - if ((sr & TIM_SR_CC3IF) != 0) + if ((sr & STM32_TIM_SR_CC3IF) != 0) PWMD8.config->channels[2].callback(&PWMD8); - if ((sr & TIM_SR_CC4IF) != 0) + if ((sr & STM32_TIM_SR_CC4IF) != 0) PWMD8.config->channels[3].callback(&PWMD8); CH_IRQ_EPILOGUE(); @@ -475,14 +475,10 @@ void pwm_lld_start(PWMDriver *pwmp) { /* All channels configured in PWM1 mode with preload enabled and will stay that way until the driver is stopped.*/ - pwmp->tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | - TIM_CCMR1_OC1PE | - TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | - TIM_CCMR1_OC2PE; - pwmp->tim->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 | - TIM_CCMR2_OC3PE | - TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | - TIM_CCMR2_OC4PE; + pwmp->tim->CCMR1 = STM32_TIM_CCMR1_OC1M(6) | STM32_TIM_CCMR1_OC1PE | + STM32_TIM_CCMR1_OC2M(6) | STM32_TIM_CCMR1_OC2PE; + pwmp->tim->CCMR2 = STM32_TIM_CCMR2_OC3M(6) | STM32_TIM_CCMR2_OC3PE | + STM32_TIM_CCMR2_OC4M(6) | STM32_TIM_CCMR2_OC4PE; } else { /* Driver re-configuration scenario, it must be stopped first.*/ @@ -509,33 +505,33 @@ void pwm_lld_start(PWMDriver *pwmp) { ccer = 0; switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC1P; + ccer |= STM32_TIM_CCER_CC1P; case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC1E; + ccer |= STM32_TIM_CCER_CC1E; default: ; } switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC2P; + ccer |= STM32_TIM_CCER_CC2P; case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC2E; + ccer |= STM32_TIM_CCER_CC2E; default: ; } switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC3P; + ccer |= STM32_TIM_CCER_CC3P; case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC3E; + ccer |= STM32_TIM_CCER_CC3E; default: ; } switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { case PWM_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC4P; + ccer |= STM32_TIM_CCER_CC4P; case PWM_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC4E; + ccer |= STM32_TIM_CCER_CC4E; default: ; } @@ -551,25 +547,25 @@ void pwm_lld_start(PWMDriver *pwmp) { #endif switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC1NP; + ccer |= STM32_TIM_CCER_CC1NP; case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC1NE; + ccer |= STM32_TIM_CCER_CC1NE; default: ; } switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC2NP; + ccer |= STM32_TIM_CCER_CC2NP; case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC2NE; + ccer |= STM32_TIM_CCER_CC2NE; default: ; } switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: - ccer |= TIM_CCER_CC3NP; + ccer |= STM32_TIM_CCER_CC3NP; case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: - ccer |= TIM_CCER_CC3NE; + ccer |= STM32_TIM_CCER_CC3NE; default: ; } @@ -577,18 +573,18 @@ void pwm_lld_start(PWMDriver *pwmp) { #endif /* STM32_PWM_USE_ADVANCED*/ pwmp->tim->CCER = ccer; - pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */ - pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : TIM_DIER_UIE; + pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ + pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE; pwmp->tim->SR = 0; /* Clear pending IRQs. */ #if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 #if STM32_PWM_USE_ADVANCED - pwmp->tim->BDTR = pwmp->config->bdtr | TIM_BDTR_MOE; + pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE; #else - pwmp->tim->BDTR = TIM_BDTR_MOE; + pwmp->tim->BDTR = STM32_TIM_BDTR_MOE; #endif #endif /* Timer configured and started.*/ - pwmp->tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; + pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; } /** diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index 98e84945d..0ef6abbca 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -25,6 +25,8 @@ #ifndef _PWM_LLD_H_ #define _PWM_LLD_H_ +#include "stm32_tim.h" + #if HAL_USE_PWM || defined(__DOXYGEN__) /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/stm32.h b/os/hal/platforms/STM32/stm32.h index b56f769b5..67dcd6eb2 100644 --- a/os/hal/platforms/STM32/stm32.h +++ b/os/hal/platforms/STM32/stm32.h @@ -87,72 +87,10 @@ /* Driver data structures and types. */ /*===========================================================================*/ -/** - * @brief STM32 TIM registers block. - * @note Redefined from the ST headers because the non uniform - * declaration of the CCR registers among the various - * sub-families. - */ -typedef struct { - volatile uint16_t CR1; - uint16_t _resvd0; - volatile uint16_t CR2; - uint16_t _resvd1; - volatile uint16_t SMCR; - uint16_t _resvd2; - volatile uint16_t DIER; - uint16_t _resvd3; - volatile uint16_t SR; - uint16_t _resvd4; - volatile uint16_t EGR; - uint16_t _resvd5; - volatile uint16_t CCMR1; - uint16_t _resvd6; - volatile uint16_t CCMR2; - uint16_t _resvd7; - volatile uint16_t CCER; - uint16_t _resvd8; - volatile uint32_t CNT; - volatile uint16_t PSC; - uint16_t _resvd9; - volatile uint32_t ARR; - volatile uint16_t RCR; - uint16_t _resvd10; - volatile uint32_t CCR[4]; - volatile uint16_t BDTR; - uint16_t _resvd11; - volatile uint16_t DCR; - uint16_t _resvd12; - volatile uint16_t DMAR; - uint16_t _resvd13; - volatile uint16_t OR; - uint16_t _resvd14; -} stm32_tim_t; - /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ -/** - * @name TIM units references - * @{ - */ -#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) -#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) -#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) -#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) -#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) -#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) -#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) -#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) -#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) -#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) -#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) -#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) -#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) -#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) -/** @} */ - /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/