diff --git a/os/hal/platforms/STM32F2xx/adc_lld.h b/os/hal/platforms/STM32F2xx/adc_lld.h
index 2b4c40b92..737fa05c9 100644
--- a/os/hal/platforms/STM32F2xx/adc_lld.h
+++ b/os/hal/platforms/STM32F2xx/adc_lld.h
@@ -46,11 +46,8 @@
 
 /**
  * @brief   Maximum HSE  clock frequency.
- * @note    This value is arbitrary defined, the current datasheet does not
- *          define a maximum value (it is TBD). A value of 36MHz is mentioned
- *          but without relationship to VDD ranges.
  */
-#define STM32_ADCCLK_MAX        42000000
+#define STM32_ADCCLK_MAX        30000000
 /** @} */
 
 /**
@@ -123,9 +120,9 @@
 /**
  * @brief   ADC common clock divider.
  * @note    This setting is influenced by the VDDA voltage and other
- *          external conditions, please refer to the STM32L15x datasheet
+ *          external conditions, please refer to the STM32F2xx datasheet
  *          for more info.<br>
- *          See section 6.3.15 "12-bit ADC characteristics".
+ *          See section 5.3.20 "12-bit ADC characteristics".
  */
 #if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
 #define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV2
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c
index 26beb1cf0..1caa61d89 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.c
+++ b/os/hal/platforms/STM32F2xx/hal_lld.c
@@ -19,8 +19,8 @@
 */
 
 /**
- * @file    STM32F4xx/hal_lld.c
- * @brief   STM32F4xx HAL subsystem low level driver source.
+ * @file    STM32F2xx/hal_lld.c
+ * @brief   STM32F2xx HAL subsystem low level driver source.
  *
  * @addtogroup HAL
  * @{
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h
index ad70d3e03..21723bd70 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.h
+++ b/os/hal/platforms/STM32F4xx/adc_lld.h
@@ -46,11 +46,8 @@
 
 /**
  * @brief   Maximum HSE  clock frequency.
- * @note    This value is arbitrary defined, the current datasheet does not
- *          define a maximum value (it is TBD). A value of 36MHz is mentioned
- *          but without relationship to VDD ranges.
  */
-#define STM32_ADCCLK_MAX        42000000
+#define STM32_ADCCLK_MAX        36000000
 /** @} */
 
 /**
@@ -123,9 +120,9 @@
 /**
  * @brief   ADC common clock divider.
  * @note    This setting is influenced by the VDDA voltage and other
- *          external conditions, please refer to the STM32L15x datasheet
+ *          external conditions, please refer to the STM32F4xx datasheet
  *          for more info.<br>
- *          See section 6.3.15 "12-bit ADC characteristics".
+ *          See section 5.3.20 "12-bit ADC characteristics".
  */
 #if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
 #define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV2
diff --git a/readme.txt b/readme.txt
index c771dc115..a948245e6 100644
--- a/readme.txt
+++ b/readme.txt
@@ -79,6 +79,9 @@
 *****************************************************************************
 
 *** 2.5.0 ***
+- FIX: Fixed various minor documentation errors and fixed ADC maximum
+  frequency limit in STM32F2/F4 ADC drivers (bug 3484942)(backported
+  to 2.4.1).
 - NEW: Updated debug plugin 1.0.8 (backported to 2.4.0).
 - NEW: Added more accurate UBRR calculation in AVR serial driver (backported
   to 2.4.0).