Fixed typos in comments.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7600 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h

@@ -71,7 +71,7 @@
 #define STM32_PLLIN_MAX         24000000
 
 /**
- * @brief   Maximum PLLs input clock frequency.
+ * @brief   Minimum PLLs input clock frequency.
  */
 #define STM32_PLLIN_MIN         1000000
 
@@ -81,7 +81,7 @@
 #define STM32_PLLOUT_MAX        24000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        16000000
 

os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h

@@ -71,7 +71,7 @@
 #define STM32_PLLIN_MAX         25000000
 
 /**
- * @brief   Maximum PLLs input clock frequency.
+ * @brief   Minimum PLLs input clock frequency.
  */
 #define STM32_PLLIN_MIN         1000000
 
@@ -81,7 +81,7 @@
 #define STM32_PLLOUT_MAX        72000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        16000000
 

os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h

@@ -71,7 +71,7 @@
 #define STM32_PLL1IN_MAX        12000000
 
 /**
- * @brief   Maximum PLL1 input clock frequency.
+ * @brief   Minimum PLL1 input clock frequency.
  */
 #define STM32_PLL1IN_MIN        3000000
 
@@ -81,7 +81,7 @@
 #define STM32_PLL23IN_MAX       5000000
 
 /**
- * @brief   Maximum PLL2 and PLL3 input clock frequency.
+ * @brief   Minimum PLL2 and PLL3 input clock frequency.
  */
 #define STM32_PLL23IN_MIN       3000000
 
@@ -91,7 +91,7 @@
 #define STM32_PLL1VCO_MAX       144000000
 
 /**
- * @brief   Maximum PLL1 VCO clock frequency.
+ * @brief   Minimum PLL1 VCO clock frequency.
  */
 #define STM32_PLL1VCO_MIN       36000000
 
@@ -101,7 +101,7 @@
 #define STM32_PLL23VCO_MAX      148000000
 
 /**
- * @brief   Maximum PLL2 and PLL3 VCO clock frequency.
+ * @brief   Minimum PLL2 and PLL3 VCO clock frequency.
  */
 #define STM32_PLL23VCO_MIN      80000000
 

os/hal/ports/STM32/STM32F37x/hal_lld.h

@@ -108,7 +108,7 @@
 #define STM32_PLLOUT_MAX        72000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        16000000
 

os/hal/ports/STM32/STM32F3xx/hal_lld.h

@@ -131,7 +131,7 @@
 #define STM32_PLLOUT_MAX        72000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        16000000
 

os/hal/ports/STM32/STM32F4xx/hal_lld.h

@@ -165,7 +165,7 @@
 #define STM32_PLLVCO_MAX        432000000
 
 /**
- * @brief   Maximum PLLs VCO clock frequency.
+ * @brief   Minimum PLLs VCO clock frequency.
  */
 #define STM32_PLLVCO_MIN        192000000