mirror of https://github.com/rusefi/ChibiOS.git
More H7 code.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11170 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
95cf891ac5
commit
e6199d4b54
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@ -18,7 +18,7 @@
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#define MCUCONF_H
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#define MCUCONF_H
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/*
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/*
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* STM32F7xx drivers configuration.
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* STM32H7xx drivers configuration.
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* The following settings override the default settings present in
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* Note that the settings for each driver only have effect if the whole
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@ -34,14 +34,15 @@
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#define STM32H7xx_MCUCONF
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#define STM32H7xx_MCUCONF
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/*
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/*
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* General settins.
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* General settings.
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*/
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_NO_INIT FALSE
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#define STM32_HCLK_ENFORCED_VALUE STM32_HSICLK
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#define STM32_HCLK_ENFORCED_VALUE STM32_HSICLK
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/*
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/*
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* PWR system settings.
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* PWR system settings.
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* Constants are taken from the ST header, reading manual is required.
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* Reading STM32 Reference Manual is required.
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* Constants are taken from the ST header.
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*/
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*/
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#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
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#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
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#define STM32_PWR_CR2 (PWR_CR2_BREN)
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#define STM32_PWR_CR2 (PWR_CR2_BREN)
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@ -51,8 +52,44 @@
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/*
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/*
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* Clock tree settings.
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* Clock tree settings.
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* Constants are taken from the ST header, reading manual is required.
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* Reading STM32 Reference Manual is required.
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*/
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*/
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_CSI_ENABLED FALSE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_HSIDIV STM32_HSIDIV_DIV1
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#define STM32_RTCPRE_VALUE 8
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLL1_ENABLED TRUE
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#define STM32_PLL1_DIVM_VALUE 4
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#define STM32_PLL1_DIVN_VALUE 400
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#define STM32_PLL1_FRACN_VALUE 0
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 8
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#define STM32_PLL1_DIVR_VALUE 8
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#define STM32_PLL2_ENABLED TRUE
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#define STM32_PLL2_DIVM_VALUE 4
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#define STM32_PLL2_DIVN_VALUE 400
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#define STM32_PLL2_FRACN_VALUE 0
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#define STM32_PLL2_DIVP_VALUE 2
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#define STM32_PLL2_DIVQ_VALUE 8
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#define STM32_PLL2_DIVR_VALUE 8
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#define STM32_PLL3_ENABLED TRUE
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#define STM32_PLL3_DIVM_VALUE 4
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#define STM32_PLL3_DIVN_VALUE 400
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#define STM32_PLL3_FRACN_VALUE 0
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#define STM32_PLL3_DIVP_VALUE 2
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#define STM32_PLL3_DIVQ_VALUE 8
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#define STM32_PLL3_DIVR_VALUE 8
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#define STM32_HSI_ENABLED TRUE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_CSI_ENABLED TRUE
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#define STM32_CSI_ENABLED TRUE
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@ -178,7 +178,7 @@
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/**
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/**
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* @brief Maximum APB3 clock frequency.
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* @brief Maximum APB3 clock frequency.
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*/
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*/
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#define STM32_PCLK3_MAX (STM32_HCLK_MAX / 1)
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#define STM32_PCLK3_MAX (STM32_HCLK_MAX / 2)
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/**
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/**
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* @brief Maximum APB4 clock frequency.
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* @brief Maximum APB4 clock frequency.
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@ -200,7 +200,7 @@
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* @name Internal clock sources
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* @name Internal clock sources
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* @{
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* @{
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*/
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*/
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#define STM32_HSICLK 16000000 /**< High speed internal clock. */
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#define STM32_HSICLK 64000000 /**< High speed internal clock. */
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#define STM32_LSICLK 32000 /**< Low speed internal clock. */
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#define STM32_LSICLK 32000 /**< Low speed internal clock. */
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/** @} */
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/** @} */
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@ -208,227 +208,69 @@
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* @name Register helpers not found in ST headers
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* @name Register helpers not found in ST headers
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* @{
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* @{
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*/
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*/
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#define RCC_CR_HSIDIV_VALUE(n) ((n) << 3U)
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#define RCC_CFGR_RTCPRE_VALUE(n) ((n) << 8U)
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#define RCC_CFGR_MCO1PRE_VALUE(n) ((n) << 18U)
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#define RCC_CFGR_MCO1_VALUE(n) ((n) << 22U)
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#define RCC_CFGR_MCO2PRE_VALUE(n) ((n) << 25U)
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#define RCC_CFGR_MCO2_VALUE(n) ((n) << 29U)
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#define RCC_PLLCKSELR_DIVM1_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM1_Pos)
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#define RCC_PLLCKSELR_DIVM1_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM1_Pos)
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#define RCC_PLLCKSELR_DIVM2_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM2_Pos)
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#define RCC_PLLCKSELR_DIVM2_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM2_Pos)
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#define RCC_PLLCKSELR_DIVM3_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM3_Pos)
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#define RCC_PLLCKSELR_DIVM3_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM3_Pos)
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#define RCC_PLL1DIVR_DIVN1_VALUE(n) ((n) << RCC_PLL1DIVR_N1)
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#define RCC_PLL1DIVR_DIVN1_VALUE(n) ((n) << RCC_PLL1DIVR_N1)
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#define RCC_PLL1DIVR_DIVP1_VALUE(n) ((n) << RCC_PLL1DIVR_P1)
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#define RCC_PLL1DIVR_DIVP1_VALUE(n) ((n) << RCC_PLL1DIVR_P1)
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#define RCC_PLL1DIVR_DIVQ1_VALUE(n) ((n) << RCC_PLL1DIVR_Q1)
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#define RCC_PLL1DIVR_DIVQ1_VALUE(n) ((n) << RCC_PLL1DIVR_Q1)
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#define RCC_PLL1DIVR_DIVR1_VALUE(n) ((n) << RCC_PLL1DIVR_R1)
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#define RCC_PLL1DIVR_DIVR1_VALUE(n) ((n) << RCC_PLL1DIVR_R1)
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#define RCC_PLL1FRACR_FRACN1_VALUE(n) ((n) << RCC_PLL1FRACR_FRACN1_Pos)
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#define RCC_PLL1FRACR_FRACN1_VALUE(n) ((n) << RCC_PLL1FRACR_FRACN1_Pos)
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#define RCC_PLL2DIVR_DIVN2_VALUE(n) ((n) << RCC_PLL2DIVR_N2)
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#define RCC_PLL2DIVR_DIVN2_VALUE(n) ((n) << RCC_PLL2DIVR_N2)
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#define RCC_PLL2DIVR_DIVP2_VALUE(n) ((n) << RCC_PLL2DIVR_P2)
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#define RCC_PLL2DIVR_DIVP2_VALUE(n) ((n) << RCC_PLL2DIVR_P2)
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#define RCC_PLL2DIVR_DIVQ2_VALUE(n) ((n) << RCC_PLL2DIVR_Q2)
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#define RCC_PLL2DIVR_DIVQ2_VALUE(n) ((n) << RCC_PLL2DIVR_Q2)
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#define RCC_PLL2DIVR_DIVR2_VALUE(n) ((n) << RCC_PLL2DIVR_R2)
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#define RCC_PLL2DIVR_DIVR2_VALUE(n) ((n) << RCC_PLL2DIVR_R2)
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#define RCC_PLL2FRACR_FRACN2_VALUE(n) ((n) << RCC_PLL2FRACR_FRACN2_Pos)
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#define RCC_PLL2FRACR_FRACN2_VALUE(n) ((n) << RCC_PLL2FRACR_FRACN2_Pos)
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#define RCC_PLL3DIVR_DIVN3_VALUE(n) ((n) << RCC_PLL3DIVR_N3)
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#define RCC_PLL3DIVR_DIVN3_VALUE(n) ((n) << RCC_PLL3DIVR_N3)
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#define RCC_PLL3DIVR_DIVP3_VALUE(n) ((n) << RCC_PLL3DIVR_P3)
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#define RCC_PLL3DIVR_DIVP3_VALUE(n) ((n) << RCC_PLL3DIVR_P3)
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#define RCC_PLL3DIVR_DIVQ3_VALUE(n) ((n) << RCC_PLL3DIVR_Q3)
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#define RCC_PLL3DIVR_DIVQ3_VALUE(n) ((n) << RCC_PLL3DIVR_Q3)
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#define RCC_PLL3DIVR_DIVR3_VALUE(n) ((n) << RCC_PLL3DIVR_R3)
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#define RCC_PLL3DIVR_DIVR3_VALUE(n) ((n) << RCC_PLL3DIVR_R3)
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#define RCC_PLL3FRACR_FRACN3_VALUE(n) ((n) << RCC_PLL3FRACR_FRACN3_Pos)
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#define RCC_PLL3FRACR_FRACN3_VALUE(n) ((n) << RCC_PLL3FRACR_FRACN3_Pos)
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#define RCC_BDCR_RTCSEL_VALUE(n) ((n) << RCC_BDCR_RTCSEL_Pos)
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/** @} */
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/** @} */
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/**
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* @name RCC_CFGR register bits definitions
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* @{
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*/
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#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
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#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
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#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
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#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */
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#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */
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#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */
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#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */
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#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */
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#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
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#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
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#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
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#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
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#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
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#define STM32_I2SSRC_OFF (1 << 23) /**< ISS clock not required. */
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#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
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#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
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#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
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#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */
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#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */
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#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */
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#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */
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#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */
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#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */
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#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */
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#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
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#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
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#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
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#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
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#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
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#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
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#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
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/**
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/**
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* @name RCC_PLLI2SCFGR register bits definitions
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* @name Configuration switches to be used in @p mcuconf.h
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* @{
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* @{
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*/
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*/
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#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
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#define STM32_HSIDIV_DIV1 RCC_CR_HSIDIV_VALUE(0)
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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#define STM32_HSIDIV_DIV2 RCC_CR_HSIDIV_VALUE(1)
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/** @} */
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#define STM32_HSIDIV_DIV4 RCC_CR_HSIDIV_VALUE(2)
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#define STM32_HSIDIV_DIV8 RCC_CR_HSIDIV_VALUE(3)
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/**
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#define STM32_MCO1_HSI_CK RCC_CFGR_MCO1_VALUE(0U)
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* @name RCC_DCKCFGR1 register bits definitions
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#define STM32_MCO1_LSE_CK RCC_CFGR_MCO1_VALUE(1U)
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* @{
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#define STM32_MCO1_HSE_CK RCC_CFGR_MCO1_VALUE(2U)
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*/
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#define STM32_MCO1_PLL1_Q_CK RCC_CFGR_MCO1_VALUE(3U)
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#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
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#define STM32_MCO1_HSI48_CK RCC_CFGR_MCO1_VALUE(4U)
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#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
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#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
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#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
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#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
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#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
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#define STM32_MCO2_SYS_CK RCC_CFGR_MCO2_VALUE(0U)
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#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
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#define STM32_MCO2_PLL2_Q_CK RCC_CFGR_MCO2_VALUE(1U)
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#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */
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#define STM32_MCO2_HSE_CK RCC_CFGR_MCO2_VALUE(2U)
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#define STM32_SAI1SEL_CKIN (2 << 20) /**< SAI1 source is I2S_CKIN. */
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#define STM32_MCO2_PLL1_P_CK RCC_CFGR_MCO2_VALUE(3U)
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#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
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#define STM32_MCO2_CSI_CK RCC_CFGR_MCO2_VALUE(4U)
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#define STM32_MCO2_LSI_CK RCC_CFGR_MCO2_VALUE(5U)
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#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
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#define STM32_RTCSEL_NOCLK RCC_BDCR_RTCSEL_VALUE(0U)
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#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */
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#define STM32_RTCSEL_LSE RCC_BDCR_RTCSEL_VALUE(1U)
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#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */
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#define STM32_RTCSEL_LSI RCC_BDCR_RTCSEL_VALUE(2U)
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#define STM32_SAI2SEL_CKIN (2 << 22) /**< SAI2 source is I2S_CKIN. */
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#define STM32_RTCSEL_HSEDIV RCC_BDCR_RTCSEL_VALUE(3U)
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#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
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#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
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#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
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#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
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/** @} */
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/**
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* @name RCC_DCKCFGR2 register bits definitions
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* @{
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*/
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#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
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#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
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#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
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|
||||||
#define STM32_USART1SEL_HSI (2 << 0) /**< USART1 source is HSI. */
|
|
||||||
#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
|
|
||||||
#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
|
|
||||||
#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
|
|
||||||
#define STM32_USART2SEL_HSI (2 << 2) /**< USART2 source is HSI. */
|
|
||||||
#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */
|
|
||||||
#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */
|
|
||||||
#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */
|
|
||||||
#define STM32_USART3SEL_HSI (2 << 4) /**< USART3 source is HSI. */
|
|
||||||
#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */
|
|
||||||
#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */
|
|
||||||
#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */
|
|
||||||
#define STM32_UART4SEL_HSI (2 << 6) /**< UART4 source is HSI. */
|
|
||||||
#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
|
|
||||||
#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
|
|
||||||
#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
|
|
||||||
#define STM32_UART5SEL_HSI (2 << 8) /**< UART5 source is HSI. */
|
|
||||||
#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_USART6SEL_MASK (3 << 10) /**< USART6SEL mask. */
|
|
||||||
#define STM32_USART6SEL_PCLK2 (0 << 10) /**< USART6 source is PCLK2. */
|
|
||||||
#define STM32_USART6SEL_SYSCLK (1 << 10) /**< USART6 source is SYSCLK. */
|
|
||||||
#define STM32_USART6SEL_HSI (2 << 10) /**< USART6 source is HSI. */
|
|
||||||
#define STM32_USART6SEL_LSE (3 << 10) /**< USART6 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_UART7SEL_MASK (3 << 12) /**< UART7 mask. */
|
|
||||||
#define STM32_UART7SEL_PCLK1 (0 << 12) /**< UART7 source is PCLK1. */
|
|
||||||
#define STM32_UART7SEL_SYSCLK (1 << 12) /**< UART7 source is SYSCLK. */
|
|
||||||
#define STM32_UART7SEL_HSI (2 << 12) /**< UART7 source is HSI. */
|
|
||||||
#define STM32_UART7SEL_LSE (3 << 12) /**< UART7 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_UART8SEL_MASK (3 << 14) /**< UART8 mask. */
|
|
||||||
#define STM32_UART8SEL_PCLK1 (0 << 14) /**< UART8 source is PCLK1. */
|
|
||||||
#define STM32_UART8SEL_SYSCLK (1 << 14) /**< UART8 source is SYSCLK. */
|
|
||||||
#define STM32_UART8SEL_HSI (2 << 14) /**< UART8 source is HSI. */
|
|
||||||
#define STM32_UART8SEL_LSE (3 << 14) /**< UART8 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_I2C1SEL_MASK (3 << 16) /**< I2C1SEL mask. */
|
|
||||||
#define STM32_I2C1SEL_PCLK1 (0 << 16) /**< I2C1 source is PCLK1. */
|
|
||||||
#define STM32_I2C1SEL_SYSCLK (1 << 16) /**< I2C1 source is SYSCLK. */
|
|
||||||
#define STM32_I2C1SEL_HSI (2 << 16) /**< I2C1 source is HSI. */
|
|
||||||
#define STM32_I2C1SEL_LSE (3 << 16) /**< I2C1 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_I2C2SEL_MASK (3 << 18) /**< I2C2SEL mask. */
|
|
||||||
#define STM32_I2C2SEL_PCLK1 (0 << 18) /**< I2C2 source is PCLK1. */
|
|
||||||
#define STM32_I2C2SEL_SYSCLK (1 << 18) /**< I2C2 source is SYSCLK. */
|
|
||||||
#define STM32_I2C2SEL_HSI (2 << 18) /**< I2C2 source is HSI. */
|
|
||||||
#define STM32_I2C2SEL_LSE (3 << 18) /**< I2C2 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_I2C3SEL_MASK (3 << 20) /**< I2C3SEL mask. */
|
|
||||||
#define STM32_I2C3SEL_PCLK1 (0 << 20) /**< I2C3 source is PCLK1. */
|
|
||||||
#define STM32_I2C3SEL_SYSCLK (1 << 20) /**< I2C3 source is SYSCLK. */
|
|
||||||
#define STM32_I2C3SEL_HSI (2 << 20) /**< I2C3 source is HSI. */
|
|
||||||
#define STM32_I2C3SEL_LSE (3 << 20) /**< I2C3 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_I2C4SEL_MASK (3 << 22) /**< I2C4SEL mask. */
|
|
||||||
#define STM32_I2C4SEL_PCLK1 (0 << 22) /**< I2C4 source is PCLK1. */
|
|
||||||
#define STM32_I2C4SEL_SYSCLK (1 << 22) /**< I2C4 source is SYSCLK. */
|
|
||||||
#define STM32_I2C4SEL_HSI (2 << 22) /**< I2C4 source is HSI. */
|
|
||||||
#define STM32_I2C4SEL_LSE (3 << 22) /**< I2C4 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_LPTIM1SEL_MASK (3 << 24) /**< LPTIM1SEL mask. */
|
|
||||||
#define STM32_LPTIM1SEL_PCLK1 (0 << 24) /**< LPTIM1 source is PCLK1. */
|
|
||||||
#define STM32_LPTIM1SEL_LSI (1 << 24) /**< LPTIM1 source is LSI. */
|
|
||||||
#define STM32_LPTIM1SEL_HSI (2 << 24) /**< LPTIM1 source is HSI. */
|
|
||||||
#define STM32_LPTIM1SEL_LSE (3 << 24) /**< LPTIM1 source is LSE. */
|
|
||||||
|
|
||||||
#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
|
|
||||||
#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
|
|
||||||
#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
|
|
||||||
|
|
||||||
#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
|
|
||||||
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
|
|
||||||
#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
|
|
||||||
|
|
||||||
#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
|
|
||||||
#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
|
|
||||||
#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
|
|
||||||
/** @} */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @name RCC_BDCR register bits definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
|
|
||||||
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
|
|
||||||
#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
|
|
||||||
#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
|
|
||||||
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
@ -530,6 +372,193 @@
|
||||||
#define STM32_LSE_ENABLED TRUE
|
#define STM32_LSE_ENABLED TRUE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HSI divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_HSIDIV) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_HSIDIV STM32_HSIDIV_DIV1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RTC HSE prescaler value.
|
||||||
|
* @note The allowed values are 2..63.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_RTCPRE_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RTC clock source.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_RTCSEL STM32_RTCSEL_LSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clock source for all PLLs.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the PLL1.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_ENABLED) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_ENABLED TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL1 DIVM divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_DIVM_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_DIVM_VALUE 4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL1 DIVN multiplier.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_DIVN_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_DIVN_VALUE 400
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL1 FRACN multiplier, zero if no fractional part.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_FRACN_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_FRACN_VALUE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL1 DIVP divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_DIVP_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_DIVP_VALUE 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL1 DIVQ divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_DIVQ_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_DIVQ_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL1 DIVR divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL1_DIVR_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL1_DIVR_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the PLL2.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_ENABLED) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_ENABLED TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL2 DIVM divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_DIVM_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_DIVM_VALUE 4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL2 DIVN multiplier.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_DIVN_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_DIVN_VALUE 400
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL2 FRACN multiplier, zero if no fractional part.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_FRACN_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_FRACN_VALUE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL2 DIVP divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_DIVP_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_DIVP_VALUE 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL2 DIVQ divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_DIVQ_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_DIVQ_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL2 DIVR divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL2_DIVR_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL2_DIVR_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the PLL3.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_ENABLED) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_ENABLED TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL3 DIVM divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_DIVM_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_DIVM_VALUE 4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL3 DIVN multiplier.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_DIVN_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_DIVN_VALUE 400
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL3 FRACN multiplier, zero if no fractional part.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_FRACN_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_FRACN_VALUE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL3 DIVP divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_DIVP_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_DIVP_VALUE 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL3 DIVQ divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_DIVQ_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_DIVQ_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PLL3 DIVR divider.
|
||||||
|
*/
|
||||||
|
#if !defined(STM32_PLL3_DIVR_VALUE) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_PLL3_DIVR_VALUE 8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Main clock source selection.
|
* @brief Main clock source selection.
|
||||||
* @note If the selected clock source is not the PLL then the PLL is not
|
* @note If the selected clock source is not the PLL then the PLL is not
|
||||||
|
|
@ -613,21 +642,6 @@
|
||||||
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC clock source.
|
|
||||||
*/
|
|
||||||
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_RTCSEL STM32_RTCSEL_LSE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC HSE prescaler value.
|
|
||||||
* @note The allowed values are 2..31.
|
|
||||||
*/
|
|
||||||
#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_RTCPRE_VALUE 25
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief MCO1 clock source value.
|
* @brief MCO1 clock source value.
|
||||||
* @note The default value outputs HSI clock on MCO1 pin.
|
* @note The default value outputs HSI clock on MCO1 pin.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue