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Fixed DWT unlock on CM7 ports. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8264 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2015-09-01 08:58:14 +00:00
parent c83eac2f28
commit ebde485b9e
2 changed files with 7 additions and 1 deletions
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3
os/nil/ports/ARMCMx/nilcore_v7m.h
View File

@ -389,6 +389,9 @@ static inline void port_init(void) {
/* DWT cycle counter enable.*/ /* DWT cycle counter enable.*/
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
#if CORTEX_MODEL == 7
DWT->LAR = 0xC5ACCE55;
#endif
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/ /* Initialization of the system vectors used by the port.*/

5
os/rt/ports/ARMCMx/chcore_v7m.h
View File

@ -388,8 +388,11 @@ static inline void port_init(void) {
/* Initializing priority grouping.*/ /* Initializing priority grouping.*/
NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT); NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
/* DWT cycle counter enable.*/ /* DWT cycle counter enable, note, the M7 requires DWT unlocking.*/
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
#if CORTEX_MODEL == 7
DWT->LAR = 0xC5ACCE55;
#endif
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/ /* Initialization of the system vectors used by the port.*/