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ChibiOS
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Scatter files symbos renamed for consistency. Now all scatter exported symbols are prefixed and postfixed by a __. Adopted "base" instead of "start" for all symbols defining the base of a memory area. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13189 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-11-23 13:51:54 +00:00
parent 5f9b81e988
commit ef5ee94dad
7 changed files with 108 additions and 92 deletions
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10
os/common/startup/ARM/compilers/GCC/crt0.S
View File

@ -87,9 +87,9 @@ Reset_Handler:
* Data initialization.
* NOTE: It assumes that the DATA size is a multiple of 4.
*/
ldr r1, =_textdata
ldr r2, =_data
ldr r3, =_edata
ldr r1, =__textdata_base__
ldr r2, =__data_base__
ldr r3, =__data_end__
dataloop:
cmp r2, r3
ldrlo r0, [r1], #4
@ -100,8 +100,8 @@ dataloop:
* NOTE: It assumes that the BSS size is a multiple of 4.
*/
mov r0, #0
ldr r1, =_bss_start
ldr r2, =_bss_end
ldr r1, =__bss_base__
ldr r2, =__bss_end__
bssloop:
cmp r1, r2
strlo r0, [r1], #4

66
os/common/startup/ARM/compilers/GCC/ld/rules.ld
View File

@ -16,30 +16,30 @@
__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
__ram0_start__ = ORIGIN(ram0);
__ram0_base__ = ORIGIN(ram0);
__ram0_size__ = LENGTH(ram0);
__ram0_end__ = __ram0_start__ + __ram0_size__;
__ram1_start__ = ORIGIN(ram1);
__ram0_end__ = __ram0_base__ + __ram0_size__;
__ram1_base__ = ORIGIN(ram1);
__ram1_size__ = LENGTH(ram1);
__ram1_end__ = __ram1_start__ + __ram1_size__;
__ram2_start__ = ORIGIN(ram2);
__ram1_end__ = __ram1_base__ + __ram1_size__;
__ram2_base__ = ORIGIN(ram2);
__ram2_size__ = LENGTH(ram2);
__ram2_end__ = __ram2_start__ + __ram2_size__;
__ram3_start__ = ORIGIN(ram3);
__ram2_end__ = __ram2_base__ + __ram2_size__;
__ram3_base__ = ORIGIN(ram3);
__ram3_size__ = LENGTH(ram3);
__ram3_end__ = __ram3_start__ + __ram3_size__;
__ram4_start__ = ORIGIN(ram4);
__ram3_end__ = __ram3_base__ + __ram3_size__;
__ram4_base__ = ORIGIN(ram4);
__ram4_size__ = LENGTH(ram4);
__ram4_end__ = __ram4_start__ + __ram4_size__;
__ram5_start__ = ORIGIN(ram5);
__ram4_end__ = __ram4_base__ + __ram4_size__;
__ram5_base__ = ORIGIN(ram5);
__ram5_size__ = LENGTH(ram5);
__ram5_end__ = __ram5_start__ + __ram5_size__;
__ram6_start__ = ORIGIN(ram6);
__ram5_end__ = __ram5_base__ + __ram5_size__;
__ram6_base__ = ORIGIN(ram6);
__ram6_size__ = LENGTH(ram6);
__ram6_end__ = __ram6_start__ + __ram6_size__;
__ram7_start__ = ORIGIN(ram7);
__ram6_end__ = __ram6_base__ + __ram6_size__;
__ram7_base__ = ORIGIN(ram7);
__ram7_size__ = LENGTH(ram7);
__ram7_end__ = __ram7_start__ + __ram7_size__;
__ram7_end__ = __ram7_base__ + __ram7_size__;
ENTRY(Reset_Handler)
@ -56,29 +56,38 @@ SECTIONS
constructors : ALIGN(4)
{
PROVIDE(__init_array_start = .);
PROVIDE(__init_array_base__ = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__init_array_end = .);
PROVIDE(__init_array_end__ = .);
} > flash
destructors : ALIGN(4)
{
PROVIDE(__fini_array_start = .);
PROVIDE(__fini_array_base__ = .);
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
PROVIDE(__fini_array_end = .);
PROVIDE(__fini_array_end__ = .);
} > flash
.text : ALIGN_WITH_INPUT
{
__text_base__ = .;
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.glue_7t)
*(.glue_7)
*(.gcc*)
__text_end__ = .;
} > flash
.rodata : ALIGN(4)
{
__rodata_base__ = .;
*(.rodata)
*(.rodata.*)
. = ALIGN(4);
__rodata_end__ = .;
} > flash
.ARM.extab :
@ -87,9 +96,9 @@ SECTIONS
} > flash
.ARM.exidx : {
PROVIDE(__exidx_start = .);
PROVIDE(__exidx_base__ = .);
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
PROVIDE(__exidx_end = .);
PROVIDE(__exidx_end__ = .);
} > flash
.eh_frame_hdr :
@ -109,7 +118,6 @@ SECTIONS
. = ALIGN(4);
_etext = .;
_textdata = _etext;
.stacks (NOLOAD) :
{
@ -125,22 +133,26 @@ SECTIONS
{
. = ALIGN(4);
PROVIDE(_data = .);
__textdata_base__ = LOADADDR(.data);
__data_base__ = .;
*(.data)
*(.data.*)
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
__data_end__ = .;
} > DATA_RAM AT > flash
.bss (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
PROVIDE(_bss_start = .);
__bss_base__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
PROVIDE(_bss_end = .);
. = ALIGN(4);
__bss_end__ = .;
PROVIDE(end = .);
} > BSS_RAM

18
os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
View File

@ -281,9 +281,9 @@ psloop:
#if CRT0_INIT_DATA == TRUE
/* Data initialization. Note, it assumes that the DATA size
is a multiple of 4 so the linker file must ensure this.*/
ldr r1, =_textdata_start
ldr r2, =_data_start
ldr r3, =_data_end
ldr r1, =__textdata_base__
ldr r2, =__data_base__
ldr r3, =__data_end__
dloop:
cmp r2, r3
ittt lo
@ -296,8 +296,8 @@ dloop:
/* BSS initialization. Note, it assumes that the DATA size
is a multiple of 4 so the linker file must ensure this.*/
movs r0, #0
ldr r1, =_bss_start
ldr r2, =_bss_end
ldr r1, =__bss_base__
ldr r2, =__bss_end__
bloop:
cmp r1, r2
itt lo
@ -315,8 +315,8 @@ bloop:
#if CRT0_CALL_CONSTRUCTORS == TRUE
/* Constructors invocation.*/
ldr r4, =__init_array_start
ldr r5, =__init_array_end
ldr r4, =__init_array_base__
ldr r5, =__init_array_end__
initloop:
cmp r4, r5
bge endinitloop
@ -331,8 +331,8 @@ endinitloop:
#if CRT0_CALL_DESTRUCTORS == TRUE
/* Destructors invocation.*/
ldr r4, =__fini_array_start
ldr r5, =__fini_array_end
ldr r4, =__fini_array_base__
ldr r5, =__fini_array_end__
finiloop:
cmp r4, r5
bge endfiniloop

16
os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld
View File

@ -25,25 +25,25 @@ SECTIONS
.xtors : ALIGN(4)
{
__init_array_start = .;
__init_array_base__ = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
__fini_array_start = .;
__init_array_end__ = .;
__fini_array_base__ = .;
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
__fini_array_end = .;
__fini_array_end__ = .;
} > XTORS_FLASH AT > XTORS_FLASH_LMA
.text : ALIGN_WITH_INPUT
{
__text_base = .;
__text_base__ = .;
*(.text)
*(.text.*)
*(.glue_7t)
*(.glue_7)
*(.gcc*)
__text_end = .;
__text_end__ = .;
} > TEXT_FLASH AT > TEXT_FLASH_LMA
.rodata : ALIGN(4)
@ -61,9 +61,9 @@ SECTIONS
} > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
.ARM.exidx : {
__exidx_start = .;
__exidx_base__ = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
__exidx_end__ = .;
} > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
.eh_frame_hdr :

10
os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld
View File

@ -20,24 +20,24 @@ SECTIONS
{
PROVIDE(_textdata = LOADADDR(.data));
PROVIDE(_data = .);
_textdata_start = LOADADDR(.data);
_data_start = .;
__textdata_base__ = LOADADDR(.data);
__data_base__ = .;
*(.data)
*(.data.*)
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
_data_end = .;
__data_end__ = .;
} > DATA_RAM AT > DATA_RAM_LMA
.bss (NOLOAD) : ALIGN(4)
{
_bss_start = .;
__bss_base__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
_bss_end = .;
__bss_end__ = .;
PROVIDE(end = .);
} > BSS_RAM
}

64
os/common/startup/ARMCMx/compilers/GCC/ld/rules_memory.ld
View File

@ -14,55 +14,55 @@
limitations under the License.
*/
__ram0_start__ = ORIGIN(ram0);
__ram0_base__ = ORIGIN(ram0);
__ram0_size__ = LENGTH(ram0);
__ram0_end__ = __ram0_start__ + __ram0_size__;
__ram1_start__ = ORIGIN(ram1);
__ram0_end__ = __ram0_base__ + __ram0_size__;
__ram1_base__ = ORIGIN(ram1);
__ram1_size__ = LENGTH(ram1);
__ram1_end__ = __ram1_start__ + __ram1_size__;
__ram2_start__ = ORIGIN(ram2);
__ram1_end__ = __ram1_base__ + __ram1_size__;
__ram2_base__ = ORIGIN(ram2);
__ram2_size__ = LENGTH(ram2);
__ram2_end__ = __ram2_start__ + __ram2_size__;
__ram3_start__ = ORIGIN(ram3);
__ram2_end__ = __ram2_base__ + __ram2_size__;
__ram3_base__ = ORIGIN(ram3);
__ram3_size__ = LENGTH(ram3);
__ram3_end__ = __ram3_start__ + __ram3_size__;
__ram4_start__ = ORIGIN(ram4);
__ram3_end__ = __ram3_base__ + __ram3_size__;
__ram4_base__ = ORIGIN(ram4);
__ram4_size__ = LENGTH(ram4);
__ram4_end__ = __ram4_start__ + __ram4_size__;
__ram5_start__ = ORIGIN(ram5);
__ram4_end__ = __ram4_base__ + __ram4_size__;
__ram5_base__ = ORIGIN(ram5);
__ram5_size__ = LENGTH(ram5);
__ram5_end__ = __ram5_start__ + __ram5_size__;
__ram6_start__ = ORIGIN(ram6);
__ram5_end__ = __ram5_base__ + __ram5_size__;
__ram6_base__ = ORIGIN(ram6);
__ram6_size__ = LENGTH(ram6);
__ram6_end__ = __ram6_start__ + __ram6_size__;
__ram7_start__ = ORIGIN(ram7);
__ram6_end__ = __ram6_base__ + __ram6_size__;
__ram7_base__ = ORIGIN(ram7);
__ram7_size__ = LENGTH(ram7);
__ram7_end__ = __ram7_start__ + __ram7_size__;
__ram7_end__ = __ram7_base__ + __ram7_size__;
__flash0_start__ = ORIGIN(flash0);
__flash0_base__ = ORIGIN(flash0);
__flash0_size__ = LENGTH(flash0);
__flash0_end__ = __flash0_start__ + __flash0_size__;
__flash1_start__ = ORIGIN(flash1);
__flash0_end__ = __flash0_base__ + __flash0_size__;
__flash1_base__ = ORIGIN(flash1);
__flash1_size__ = LENGTH(flash1);
__flash1_end__ = __flash1_start__ + __flash1_size__;
__flash2_start__ = ORIGIN(flash2);
__flash1_end__ = __flash1_base__ + __flash1_size__;
__flash2_base__ = ORIGIN(flash2);
__flash2_size__ = LENGTH(flash2);
__flash2_end__ = __flash2_start__ + __flash2_size__;
__flash3_start__ = ORIGIN(flash3);
__flash2_end__ = __flash2_base__ + __flash2_size__;
__flash3_base__ = ORIGIN(flash3);
__flash3_size__ = LENGTH(flash3);
__flash3_end__ = __flash3_start__ + __flash3_size__;
__flash4_start__ = ORIGIN(flash4);
__flash3_end__ = __flash3_base__ + __flash3_size__;
__flash4_base__ = ORIGIN(flash4);
__flash4_size__ = LENGTH(flash4);
__flash4_end__ = __flash4_start__ + __flash4_size__;
__flash5_start__ = ORIGIN(flash5);
__flash4_end__ = __flash4_base__ + __flash4_size__;
__flash5_base__ = ORIGIN(flash5);
__flash5_size__ = LENGTH(flash5);
__flash5_end__ = __flash5_start__ + __flash5_size__;
__flash6_start__ = ORIGIN(flash6);
__flash5_end__ = __flash5_base__ + __flash5_size__;
__flash6_base__ = ORIGIN(flash6);
__flash6_size__ = LENGTH(flash6);
__flash6_end__ = __flash6_start__ + __flash6_size__;
__flash7_start__ = ORIGIN(flash7);
__flash6_end__ = __flash6_base__ + __flash6_size__;
__flash7_base__ = ORIGIN(flash7);
__flash7_size__ = LENGTH(flash7);
__flash7_end__ = __flash7_start__ + __flash7_size__;
__flash7_end__ = __flash7_base__ + __flash7_size__;
SECTIONS
{

16
test/lib/ch_test.c
View File

@ -257,18 +257,22 @@ msg_t test_execute(BaseSequentialStream *stream, const testsuite_t *tsp) {
#endif
#if defined(TEST_CFG_SIZE_REPORT)
{
extern uint8_t __text_base, __text_end,
_data_start, _data_end,
_bss_start, _bss_end;
extern uint8_t __text_base__, __text_end__,
__rodata_base__, __rodata_end__,
__data_base__, __data_end__,
__bss_base__, __bss_end__;
test_println("***");
test_print("*** Text size: ");
test_printn((uint32_t)(&__text_end - &__text_base));
test_printn((uint32_t)(&__text_end__ - &__text_base__));
test_println(" bytes");
test_print("*** RO data size: ");
test_printn((uint32_t)(&__rodata_end__ - &__rodata_base__));
test_println(" bytes");
test_print("*** Data size: ");
test_printn((uint32_t)(&_data_end - &_data_start));
test_printn((uint32_t)(&__data_end__ - &__data_base__));
test_println(" bytes");
test_print("*** BSS size: ");
test_printn((uint32_t)(&_bss_end - &_bss_start));
test_printn((uint32_t)(&__bss_end__ - &__bss_base__));
test_println(" bytes");
}
#endif