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SPC560Dxx support added. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5847 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2013-06-13 13:35:10 +00:00
parent 02b1b936d9
commit f0e62eb4b5
16 changed files with 6532 additions and 259 deletions
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5
demos/PPC-SPC560B-GCC/main.c
View File

@ -172,6 +172,11 @@ int main(void) {
halInit();
chSysInit();
/*
* Shell manager initialization.
*/
shellInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/

19
demos/PPC-SPC560D-GCC/main.c
View File

@ -15,12 +15,11 @@
*/
#include "ch.h"
//#include "hal.h"
//#include "test.h"
//#include "shell.h"
//#include "chprintf.h"
#include "hal.h"
#include "test.h"
#include "shell.h"
#include "chprintf.h"
#if 0
#define SHELL_WA_SIZE THD_WA_SIZE(1024)
#define TEST_WA_SIZE THD_WA_SIZE(256)
@ -86,7 +85,6 @@ static const ShellConfig shell_cfg1 = {
(BaseSequentialStream *)&SD1,
commands
};
#endif
/*
* LEDs blinker thread, times are in milliseconds.
@ -162,7 +160,7 @@ static msg_t Thread1(void *arg) {
* Application entry point.
*/
int main(void) {
// Thread *shelltp = NULL;
Thread *shelltp = NULL;
/*
* System initializations.
@ -174,6 +172,11 @@ int main(void) {
halInit();
chSysInit();
/*
* Shell manager initialization.
*/
shellInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
@ -188,14 +191,12 @@ int main(void) {
* Normal main() thread activity.
*/
while (TRUE) {
#if 0
if (!shelltp)
shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
else if (chThdTerminated(shelltp)) {
chThdRelease(shelltp); /* Recovers memory of the previous shell. */
shelltp = NULL; /* Triggers spawning of a new shell. */
}
#endif
chThdSleepMilliseconds(1000);
}
return 0;

4
demos/PPC-SPC560D-GCC/mcuconf.h
View File

@ -34,8 +34,8 @@
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_DISABLE_WATCHDOG TRUE
#define SPC5_FMPLL0_IDF_VALUE 1
#define SPC5_FMPLL0_NDIV_VALUE 32
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#define SPC5_FMPLL0_NDIV_VALUE 48
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8
#define SPC5_XOSCDIV_VALUE 1
#define SPC5_IRCDIV_VALUE 1
#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2

10
demos/PPC-SPC563M-GCC/main.c
View File

@ -134,16 +134,16 @@ int main(void) {
halInit();
chSysInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Shell manager initialization.
*/
shellInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Creates the blinker thread.
*/

10
demos/PPC-SPC564A-GCC/main.c
View File

@ -134,16 +134,16 @@ int main(void) {
halInit();
chSysInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Shell manager initialization.
*/
shellInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Creates the blinker thread.
*/

14
os/hal/platforms/SPC560Dxx/hal_lld.c
View File

@ -146,9 +146,9 @@ void spc_clock_init(void) {
#endif /* SPC5_OSC_BYPASS */
/* Setting the various dividers and source selectors.*/
CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
CGM.SC_DC1.R = SPC5_CGM_SC_DC1;
CGM.SC_DC2.R = SPC5_CGM_SC_DC2;
/* Initialization of the FMPLLs settings.*/
CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
@ -166,10 +166,10 @@ void spc_clock_init(void) {
ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
if (ME.IS.B.I_CONF) {
ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
if (ME.IS.B.I_ICONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}

2
os/hal/platforms/SPC560Dxx/hal_lld.h
View File

@ -628,7 +628,7 @@
/*
* Configuration-related checks.
*/
#if !defined(SPC560BCxx_MCUCONF)
#if !defined(SPC560Dxx_MCUCONF)
#error "Using a wrong mcuconf.h file, SPC560Dxx_MCUCONF not defined"
#endif

4
os/hal/platforms/SPC560Dxx/spc560d_registry.h
View File

@ -106,9 +106,9 @@
#define SPC5_HAS_SIUL TRUE
#define SPC5_SIUL_PCTL 68
#define SPC5_SIUL_NUM_PORTS 8
#define SPC5_SIUL_NUM_PCRS 123
#define SPC5_SIUL_NUM_PCRS 77
#define SPC5_SIUL_NUM_PADSELS 63
#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
#define SPC5_SIUL_SYSTEM_PINS 32,33
/** @} */
#endif /* _SPC560D_REGISTRY_H_ */

5557
os/hal/platforms/SPC560Dxx/xpc560d.h Normal file
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File diff suppressed because it is too large Load Diff

167
os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h
View File

@ -29,6 +29,173 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name MCR register definitions
* @{
*/
#define SPC5_MCR_MSTR (1U << 31)
#define SPC5_MCR_CONT_SCKE (1U << 30)
#define SPC5_MCR_DCONF_MASK (3U << 28)
#define SPC5_MCR_FRZ (1U << 27)
#define SPC5_MCR_MTFE (1U << 26)
#define SPC5_MCR_PCSSE (1U << 25)
#define SPC5_MCR_ROOE (1U << 24)
#define SPC5_MCR_PCSIS7 (1U << 23)
#define SPC5_MCR_PCSIS6 (1U << 22)
#define SPC5_MCR_PCSIS5 (1U << 21)
#define SPC5_MCR_PCSIS4 (1U << 20)
#define SPC5_MCR_PCSIS3 (1U << 19)
#define SPC5_MCR_PCSIS2 (1U << 18)
#define SPC5_MCR_PCSIS1 (1U << 17)
#define SPC5_MCR_PCSIS0 (1U << 16)
#define SPC5_MCR_DOZE (1U << 15)
#define SPC5_MCR_MDIS (1U << 14)
#define SPC5_MCR_DIS_TXF (1U << 13)
#define SPC5_MCR_DIS_RXF (1U << 12)
#define SPC5_MCR_CLR_TXF (1U << 11)
#define SPC5_MCR_CLR_RXF (1U << 10)
#define SPC5_MCR_SMPL_PT_MASK (3U << 8)
#define SPC5_MCR_SMPL_PT(n) ((n) << 8)
#define SPC5_MCR_FCPCS (1U << 2)
#define SPC5_MCR_PES (1U << 1)
#define SPC5_MCR_HALT (1U << 0)
/** @} */
/**
* @name RSER register definitions
* @{
*/
#define SPC5_RSER_TCF_RE (1U << 31)
#define SPC5_RSER_DSITCF_RE (1U << 29)
#define SPC5_RSER_EOQF_RE (1U << 28)
#define SPC5_RSER_TFUF_RE (1U << 27)
#define SPC5_RSER_SPITCF_RE (1U << 26)
#define SPC5_RSER_TFFF_RE (1U << 25)
#define SPC5_RSER_TFFF_DIRS (1U << 24)
#define SPC5_RSER_DPEF_RE (1U << 22)
#define SPC5_RSER_SPEF_RE (1U << 21)
#define SPC5_RSER_DDIF_RE (1U << 20)
#define SPC5_RSER_RFOF_RE (1U << 19)
#define SPC5_RSER_RFDF_RE (1U << 17)
#define SPC5_RSER_RFDF_DIRS (1U << 16)
/** @} */
/**
* @name CTAR registers definitions
* @{
*/
#define SPC5_CTAR_DBR (1U << 31)
#define SPC5_CTAR_FMSZ_MASK (15U << 27)
#define SPC5_CTAR_FMSZ(n) (((n) - 1) << 27)
#define SPC5_CTAR_CPOL (1U << 26)
#define SPC5_CTAR_CPHA (1U << 25)
#define SPC5_CTAR_LSBFE (1U << 24)
#define SPC5_CTAR_PCSSCK_MASK (3U << 22)
#define SPC5_CTAR_PCSSCK_PRE1 (0U << 22)
#define SPC5_CTAR_PCSSCK_PRE3 (1U << 22)
#define SPC5_CTAR_PCSSCK_PRE5 (2U << 22)
#define SPC5_CTAR_PCSSCK_PRE7 (3U << 22)
#define SPC5_CTAR_PASC_MASK (3U << 20)
#define SPC5_CTAR_PASC_PRE1 (0U << 20)
#define SPC5_CTAR_PASC_PRE3 (1U << 20)
#define SPC5_CTAR_PASC_PRE5 (2U << 20)
#define SPC5_CTAR_PASC_PRE7 (3U << 20)
#define SPC5_CTAR_PDT_MASK (3U << 18)
#define SPC5_CTAR_PDT_PRE1 (0U << 18)
#define SPC5_CTAR_PDT_PRE3 (1U << 18)
#define SPC5_CTAR_PDT_PRE5 (2U << 18)
#define SPC5_CTAR_PDT_PRE7 (3U << 18)
#define SPC5_CTAR_PBR_MASK (3U << 16)
#define SPC5_CTAR_PBR_PRE2 (0U << 16)
#define SPC5_CTAR_PBR_PRE3 (1U << 16)
#define SPC5_CTAR_PBR_PRE5 (2U << 16)
#define SPC5_CTAR_PBR_PRE7 (3U << 16)
#define SPC5_CTAR_CSSCK_MASK (15U << 12)
#define SPC5_CTAR_CSSCK_DIV2 (0U << 12)
#define SPC5_CTAR_CSSCK_DIV4 (1U << 12)
#define SPC5_CTAR_CSSCK_DIV6 (2U << 12)
#define SPC5_CTAR_CSSCK_DIV8 (3U << 12)
#define SPC5_CTAR_CSSCK_DIV16 (4U << 12)
#define SPC5_CTAR_CSSCK_DIV32 (5U << 12)
#define SPC5_CTAR_CSSCK_DIV64 (6U << 12)
#define SPC5_CTAR_CSSCK_DIV128 (7U << 12)
#define SPC5_CTAR_CSSCK_DIV256 (8U << 12)
#define SPC5_CTAR_CSSCK_DIV512 (9U << 12)
#define SPC5_CTAR_CSSCK_DIV1024 (10U << 12)
#define SPC5_CTAR_CSSCK_DIV2048 (11U << 12)
#define SPC5_CTAR_CSSCK_DIV4096 (12U << 12)
#define SPC5_CTAR_CSSCK_DIV8192 (13U << 12)
#define SPC5_CTAR_CSSCK_DIV16384 (14U << 12)
#define SPC5_CTAR_CSSCK_DIV32768 (15U << 12)
#define SPC5_CTAR_ASC_MASK (15U << 8)
#define SPC5_CTAR_ASC_DIV2 (0U << 8)
#define SPC5_CTAR_ASC_DIV4 (1U << 8)
#define SPC5_CTAR_ASC_DIV6 (2U << 8)
#define SPC5_CTAR_ASC_DIV8 (3U << 8)
#define SPC5_CTAR_ASC_DIV16 (4U << 8)
#define SPC5_CTAR_ASC_DIV32 (5U << 8)
#define SPC5_CTAR_ASC_DIV64 (6U << 8)
#define SPC5_CTAR_ASC_DIV128 (7U << 8)
#define SPC5_CTAR_ASC_DIV256 (8U << 8)
#define SPC5_CTAR_ASC_DIV512 (9U << 8)
#define SPC5_CTAR_ASC_DIV1024 (10U << 8)
#define SPC5_CTAR_ASC_DIV2048 (11U << 8)
#define SPC5_CTAR_ASC_DIV4096 (12U << 8)
#define SPC5_CTAR_ASC_DIV8192 (13U << 8)
#define SPC5_CTAR_ASC_DIV16384 (14U << 8)
#define SPC5_CTAR_ASC_DIV32768 (15U << 8)
#define SPC5_CTAR_DT_MASK (15U << 4)
#define SPC5_CTAR_DT_DIV2 (0U << 4)
#define SPC5_CTAR_DT_DIV4 (1U << 4)
#define SPC5_CTAR_DT_DIV6 (2U << 4)
#define SPC5_CTAR_DT_DIV8 (3U << 4)
#define SPC5_CTAR_DT_DIV16 (4U << 4)
#define SPC5_CTAR_DT_DIV32 (5U << 4)
#define SPC5_CTAR_DT_DIV64 (6U << 4)
#define SPC5_CTAR_DT_DIV128 (7U << 4)
#define SPC5_CTAR_DT_DIV256 (8U << 4)
#define SPC5_CTAR_DT_DIV512 (9U << 4)
#define SPC5_CTAR_DT_DIV1024 (10U << 4)
#define SPC5_CTAR_DT_DIV2048 (11U << 4)
#define SPC5_CTAR_DT_DIV4096 (12U << 4)
#define SPC5_CTAR_DT_DIV8192 (13U << 4)
#define SPC5_CTAR_DT_DIV16384 (14U << 4)
#define SPC5_CTAR_DT_DIV32768 (15U << 4)
#define SPC5_CTAR_BR_MASK (15U << 0)
#define SPC5_CTAR_BR_DIV2 (0U << 0)
#define SPC5_CTAR_BR_DIV4 (1U << 0)
#define SPC5_CTAR_BR_DIV6 (2U << 0)
#define SPC5_CTAR_BR_DIV8 (3U << 0)
#define SPC5_CTAR_BR_DIV16 (4U << 0)
#define SPC5_CTAR_BR_DIV32 (5U << 0)
#define SPC5_CTAR_BR_DIV64 (6U << 0)
#define SPC5_CTAR_BR_DIV128 (7U << 0)
#define SPC5_CTAR_BR_DIV256 (8U << 0)
#define SPC5_CTAR_BR_DIV512 (9U << 0)
#define SPC5_CTAR_BR_DIV1024 (10U << 0)
#define SPC5_CTAR_BR_DIV2048 (11U << 0)
#define SPC5_CTAR_BR_DIV4096 (12U << 0)
#define SPC5_CTAR_BR_DIV8192 (13U << 0)
#define SPC5_CTAR_BR_DIV16384 (14U << 0)
#define SPC5_CTAR_BR_DIV32768 (15U << 0)
/** @} */
/**
* @name PUSHR register definitions
* @{
*/
#define SPC5_PUSHR_CONT (1U << 31)
#define SPC5_PUSHR_CTAS_MASK (3U << 28)
#define SPC5_PUSHR_CTAS(n) ((n) << 29)
#define SPC5_PUSHR_EOQ (1U << 27)
#define SPC5_PUSHR_CTCNT (1U << 26)
#define SPC5_PUSHR_MASC (1U << 25)
#define SPC5_PUSHR_MCSC (1U << 24)
#define SPC5_PUSHR_PCS_MASK (255U << 16)
#define SPC5_PUSHR_PCS(n) ((1U << (n)) << 16)
#define SPC5_PUSHR_TXDATA_MASK (0xFFFFU << 0)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/

167
os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
View File

@ -33,173 +33,6 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name MCR register definitions
* @{
*/
#define SPC5_MCR_MSTR (1U << 31)
#define SPC5_MCR_CONT_SCKE (1U << 30)
#define SPC5_MCR_DCONF_MASK (3U << 28)
#define SPC5_MCR_FRZ (1U << 27)
#define SPC5_MCR_MTFE (1U << 26)
#define SPC5_MCR_PCSSE (1U << 25)
#define SPC5_MCR_ROOE (1U << 24)
#define SPC5_MCR_PCSIS7 (1U << 23)
#define SPC5_MCR_PCSIS6 (1U << 22)
#define SPC5_MCR_PCSIS5 (1U << 21)
#define SPC5_MCR_PCSIS4 (1U << 20)
#define SPC5_MCR_PCSIS3 (1U << 19)
#define SPC5_MCR_PCSIS2 (1U << 18)
#define SPC5_MCR_PCSIS1 (1U << 17)
#define SPC5_MCR_PCSIS0 (1U << 16)
#define SPC5_MCR_DOZE (1U << 15)
#define SPC5_MCR_MDIS (1U << 14)
#define SPC5_MCR_DIS_TXF (1U << 13)
#define SPC5_MCR_DIS_RXF (1U << 12)
#define SPC5_MCR_CLR_TXF (1U << 11)
#define SPC5_MCR_CLR_RXF (1U << 10)
#define SPC5_MCR_SMPL_PT_MASK (3U << 8)
#define SPC5_MCR_SMPL_PT(n) ((n) << 8)
#define SPC5_MCR_FCPCS (1U << 2)
#define SPC5_MCR_PES (1U << 1)
#define SPC5_MCR_HALT (1U << 0)
/** @} */
/**
* @name RSER register definitions
* @{
*/
#define SPC5_RSER_TCF_RE (1U << 31)
#define SPC5_RSER_DSITCF_RE (1U << 29)
#define SPC5_RSER_EOQF_RE (1U << 28)
#define SPC5_RSER_TFUF_RE (1U << 27)
#define SPC5_RSER_SPITCF_RE (1U << 26)
#define SPC5_RSER_TFFF_RE (1U << 25)
#define SPC5_RSER_TFFF_DIRS (1U << 24)
#define SPC5_RSER_DPEF_RE (1U << 22)
#define SPC5_RSER_SPEF_RE (1U << 21)
#define SPC5_RSER_DDIF_RE (1U << 20)
#define SPC5_RSER_RFOF_RE (1U << 19)
#define SPC5_RSER_RFDF_RE (1U << 17)
#define SPC5_RSER_RFDF_DIRS (1U << 16)
/** @} */
/**
* @name CTAR registers definitions
* @{
*/
#define SPC5_CTAR_DBR (1U << 31)
#define SPC5_CTAR_FMSZ_MASK (15U << 27)
#define SPC5_CTAR_FMSZ(n) (((n) - 1) << 27)
#define SPC5_CTAR_CPOL (1U << 26)
#define SPC5_CTAR_CPHA (1U << 25)
#define SPC5_CTAR_LSBFE (1U << 24)
#define SPC5_CTAR_PCSSCK_MASK (3U << 22)
#define SPC5_CTAR_PCSSCK_PRE1 (0U << 22)
#define SPC5_CTAR_PCSSCK_PRE3 (1U << 22)
#define SPC5_CTAR_PCSSCK_PRE5 (2U << 22)
#define SPC5_CTAR_PCSSCK_PRE7 (3U << 22)
#define SPC5_CTAR_PASC_MASK (3U << 20)
#define SPC5_CTAR_PASC_PRE1 (0U << 20)
#define SPC5_CTAR_PASC_PRE3 (1U << 20)
#define SPC5_CTAR_PASC_PRE5 (2U << 20)
#define SPC5_CTAR_PASC_PRE7 (3U << 20)
#define SPC5_CTAR_PDT_MASK (3U << 18)
#define SPC5_CTAR_PDT_PRE1 (0U << 18)
#define SPC5_CTAR_PDT_PRE3 (1U << 18)
#define SPC5_CTAR_PDT_PRE5 (2U << 18)
#define SPC5_CTAR_PDT_PRE7 (3U << 18)
#define SPC5_CTAR_PBR_MASK (3U << 16)
#define SPC5_CTAR_PBR_PRE2 (0U << 16)
#define SPC5_CTAR_PBR_PRE3 (1U << 16)
#define SPC5_CTAR_PBR_PRE5 (2U << 16)
#define SPC5_CTAR_PBR_PRE7 (3U << 16)
#define SPC5_CTAR_CSSCK_MASK (15U << 12)
#define SPC5_CTAR_CSSCK_DIV2 (0U << 12)
#define SPC5_CTAR_CSSCK_DIV4 (1U << 12)
#define SPC5_CTAR_CSSCK_DIV6 (2U << 12)
#define SPC5_CTAR_CSSCK_DIV8 (3U << 12)
#define SPC5_CTAR_CSSCK_DIV16 (4U << 12)
#define SPC5_CTAR_CSSCK_DIV32 (5U << 12)
#define SPC5_CTAR_CSSCK_DIV64 (6U << 12)
#define SPC5_CTAR_CSSCK_DIV128 (7U << 12)
#define SPC5_CTAR_CSSCK_DIV256 (8U << 12)
#define SPC5_CTAR_CSSCK_DIV512 (9U << 12)
#define SPC5_CTAR_CSSCK_DIV1024 (10U << 12)
#define SPC5_CTAR_CSSCK_DIV2048 (11U << 12)
#define SPC5_CTAR_CSSCK_DIV4096 (12U << 12)
#define SPC5_CTAR_CSSCK_DIV8192 (13U << 12)
#define SPC5_CTAR_CSSCK_DIV16384 (14U << 12)
#define SPC5_CTAR_CSSCK_DIV32768 (15U << 12)
#define SPC5_CTAR_ASC_MASK (15U << 8)
#define SPC5_CTAR_ASC_DIV2 (0U << 8)
#define SPC5_CTAR_ASC_DIV4 (1U << 8)
#define SPC5_CTAR_ASC_DIV6 (2U << 8)
#define SPC5_CTAR_ASC_DIV8 (3U << 8)
#define SPC5_CTAR_ASC_DIV16 (4U << 8)
#define SPC5_CTAR_ASC_DIV32 (5U << 8)
#define SPC5_CTAR_ASC_DIV64 (6U << 8)
#define SPC5_CTAR_ASC_DIV128 (7U << 8)
#define SPC5_CTAR_ASC_DIV256 (8U << 8)
#define SPC5_CTAR_ASC_DIV512 (9U << 8)
#define SPC5_CTAR_ASC_DIV1024 (10U << 8)
#define SPC5_CTAR_ASC_DIV2048 (11U << 8)
#define SPC5_CTAR_ASC_DIV4096 (12U << 8)
#define SPC5_CTAR_ASC_DIV8192 (13U << 8)
#define SPC5_CTAR_ASC_DIV16384 (14U << 8)
#define SPC5_CTAR_ASC_DIV32768 (15U << 8)
#define SPC5_CTAR_DT_MASK (15U << 4)
#define SPC5_CTAR_DT_DIV2 (0U << 4)
#define SPC5_CTAR_DT_DIV4 (1U << 4)
#define SPC5_CTAR_DT_DIV6 (2U << 4)
#define SPC5_CTAR_DT_DIV8 (3U << 4)
#define SPC5_CTAR_DT_DIV16 (4U << 4)
#define SPC5_CTAR_DT_DIV32 (5U << 4)
#define SPC5_CTAR_DT_DIV64 (6U << 4)
#define SPC5_CTAR_DT_DIV128 (7U << 4)
#define SPC5_CTAR_DT_DIV256 (8U << 4)
#define SPC5_CTAR_DT_DIV512 (9U << 4)
#define SPC5_CTAR_DT_DIV1024 (10U << 4)
#define SPC5_CTAR_DT_DIV2048 (11U << 4)
#define SPC5_CTAR_DT_DIV4096 (12U << 4)
#define SPC5_CTAR_DT_DIV8192 (13U << 4)
#define SPC5_CTAR_DT_DIV16384 (14U << 4)
#define SPC5_CTAR_DT_DIV32768 (15U << 4)
#define SPC5_CTAR_BR_MASK (15U << 0)
#define SPC5_CTAR_BR_DIV2 (0U << 0)
#define SPC5_CTAR_BR_DIV4 (1U << 0)
#define SPC5_CTAR_BR_DIV6 (2U << 0)
#define SPC5_CTAR_BR_DIV8 (3U << 0)
#define SPC5_CTAR_BR_DIV16 (4U << 0)
#define SPC5_CTAR_BR_DIV32 (5U << 0)
#define SPC5_CTAR_BR_DIV64 (6U << 0)
#define SPC5_CTAR_BR_DIV128 (7U << 0)
#define SPC5_CTAR_BR_DIV256 (8U << 0)
#define SPC5_CTAR_BR_DIV512 (9U << 0)
#define SPC5_CTAR_BR_DIV1024 (10U << 0)
#define SPC5_CTAR_BR_DIV2048 (11U << 0)
#define SPC5_CTAR_BR_DIV4096 (12U << 0)
#define SPC5_CTAR_BR_DIV8192 (13U << 0)
#define SPC5_CTAR_BR_DIV16384 (14U << 0)
#define SPC5_CTAR_BR_DIV32768 (15U << 0)
/** @} */
/**
* @name PUSHR register definitions
* @{
*/
#define SPC5_PUSHR_CONT (1U << 31)
#define SPC5_PUSHR_CTAS_MASK (3U << 28)
#define SPC5_PUSHR_CTAS(n) ((n) << 29)
#define SPC5_PUSHR_EOQ (1U << 27)
#define SPC5_PUSHR_CTCNT (1U << 26)
#define SPC5_PUSHR_MASC (1U << 25)
#define SPC5_PUSHR_MCSC (1U << 24)
#define SPC5_PUSHR_PCS_MASK (255U << 16)
#define SPC5_PUSHR_PCS(n) ((1U << (n)) << 16)
#define SPC5_PUSHR_TXDATA_MASK (0xFFFFU << 0)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/

2
os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
View File

@ -15,7 +15,7 @@
*/
/**
* @file SPC5xx/edma.c
* @file SPC5xx/spc5_edma.c
* @brief EDMA helper driver code.
*
* @addtogroup SPC5xx_EDMA

2
os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
View File

@ -15,7 +15,7 @@
*/
/**
* @file SPC5xx/edma.h
* @file SPC5xx/spc5_edma.h
* @brief EDMA helper driver header.
*
* @addtogroup SPC5xx_EDMA

184
os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
View File

@ -84,7 +84,7 @@ static const SerialConfig default_config = {
*/
static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
uint32_t div;
volatile struct LINFLEX_tag *linflexp = sdp->linflexp;
volatile struct spc5_linflex *linflexp = sdp->linflexp;
/* Enters the configuration mode.*/
linflexp->LINCR1.R = 1; /* INIT bit. */
@ -111,7 +111,7 @@ static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
*
* @param[in] linflexp pointer to a LINFlex I/O block
*/
static void spc5_linflex_deinit(volatile struct LINFLEX_tag *linflexp) {
static void spc5_linflex_deinit(volatile struct spc5_linflex *linflexp) {
/* Enters the configuration mode.*/
linflexp->LINCR1.R = 1; /* INIT bit. */
@ -222,6 +222,34 @@ static void notify2(GenericQueue *qp) {
}
#endif
#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
static void notify3(GenericQueue *qp) {
(void)qp;
if (!SD3.linflexp->UARTCR.B.TXEN) {
msg_t b = sdRequestDataI(&SD3);
if (b != Q_EMPTY) {
SD3.linflexp->UARTCR.B.TXEN = 1;
SD3.linflexp->BDRL.B.DATA0 = b;
}
}
}
#endif
#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
static void notify4(GenericQueue *qp) {
(void)qp;
if (!SD4.linflexp->UARTCR.B.TXEN) {
msg_t b = sdRequestDataI(&SD4);
if (b != Q_EMPTY) {
SD4.linflexp->UARTCR.B.TXEN = 1;
SD4.linflexp->BDRL.B.DATA0 = b;
}
}
}
#endif
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@ -332,6 +360,112 @@ CH_IRQ_HANDLER(SPC5_LINFLEX1_ERR_HANDLER) {
}
#endif
#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
#if !defined(SPC5_LINFLEX2_RXI_HANDLER)
#error "SPC5_LINFLEX2_RXI_HANDLER not defined"
#endif
/**
* @brief LINFlex-2 RXI interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(SPC5_LINFLEX2_RXI_HANDLER) {
CH_IRQ_PROLOGUE();
spc5xx_serve_rxi_interrupt(&SD3);
CH_IRQ_EPILOGUE();
}
#if !defined(SPC5_LINFLEX2_TXI_HANDLER)
#error "SPC5_LINFLEX2_TXI_HANDLER not defined"
#endif
/**
* @brief LINFlex-2 TXI interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(SPC5_LINFLEX2_TXI_HANDLER) {
CH_IRQ_PROLOGUE();
spc5xx_serve_txi_interrupt(&SD3);
CH_IRQ_EPILOGUE();
}
#if !defined(SPC5_LINFLEX2_ERR_HANDLER)
#error "SPC5_LINFLEX2_ERR_HANDLER not defined"
#endif
/**
* @brief LINFlex-2 ERR interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(SPC5_LINFLEX2_ERR_HANDLER) {
CH_IRQ_PROLOGUE();
spc5xx_serve_err_interrupt(&SD3);
CH_IRQ_EPILOGUE();
}
#endif
#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
#if !defined(SPC5_LINFLEX3_RXI_HANDLER)
#error "SPC5_LINFLEX3_RXI_HANDLER not defined"
#endif
/**
* @brief LINFlex-3 RXI interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(SPC5_LINFLEX3_RXI_HANDLER) {
CH_IRQ_PROLOGUE();
spc5xx_serve_rxi_interrupt(&SD4);
CH_IRQ_EPILOGUE();
}
#if !defined(SPC5_LINFLEX3_TXI_HANDLER)
#error "SPC5_LINFLEX3_TXI_HANDLER not defined"
#endif
/**
* @brief LINFlex-3 TXI interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(SPC5_LINFLEX3_TXI_HANDLER) {
CH_IRQ_PROLOGUE();
spc5xx_serve_txi_interrupt(&SD4);
CH_IRQ_EPILOGUE();
}
#if !defined(SPC5_LINFLEX3_ERR_HANDLER)
#error "SPC5_LINFLEX3_ERR_HANDLER not defined"
#endif
/**
* @brief LINFlex-3 ERR interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(SPC5_LINFLEX3_ERR_HANDLER) {
CH_IRQ_PROLOGUE();
spc5xx_serve_err_interrupt(&SD4);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -345,7 +479,7 @@ void sd_lld_init(void) {
#if SPC5_SERIAL_USE_LINFLEX0
sdObjectInit(&SD1, NULL, notify1);
SD1.linflexp = &LINFLEX_0;
SD1.linflexp = &SPC5_LINFLEX0;
INTC.PSR[SPC5_LINFLEX0_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
INTC.PSR[SPC5_LINFLEX0_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
INTC.PSR[SPC5_LINFLEX0_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
@ -353,11 +487,27 @@ void sd_lld_init(void) {
#if SPC5_SERIAL_USE_LINFLEX1
sdObjectInit(&SD2, NULL, notify2);
SD2.linflexp = &LINFLEX_1;
SD2.linflexp = &SPC5_LINFLEX1;
INTC.PSR[SPC5_LINFLEX1_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
INTC.PSR[SPC5_LINFLEX1_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
INTC.PSR[SPC5_LINFLEX1_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
#endif
#if SPC5_SERIAL_USE_LINFLEX2
sdObjectInit(&SD3, NULL, notify3);
SD3.linflexp = &SPC5_LINFLEX2;
INTC.PSR[SPC5_LINFLEX2_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
INTC.PSR[SPC5_LINFLEX2_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
INTC.PSR[SPC5_LINFLEX2_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
#endif
#if SPC5_SERIAL_USE_LINFLEX3
sdObjectInit(&SD4, NULL, notify4);
SD4.linflexp = &SPC5_LINFLEX3;
INTC.PSR[SPC5_LINFLEX3_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
INTC.PSR[SPC5_LINFLEX3_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
INTC.PSR[SPC5_LINFLEX3_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
#endif
}
/**
@ -387,6 +537,18 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
SPC5_SERIAL_LINFLEX1_START_PCTL);
}
#endif
#if SPC5_SERIAL_USE_LINFLEX2
if (&SD3 == sdp) {
halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
SPC5_SERIAL_LINFLEX2_START_PCTL);
}
#endif
#if SPC5_SERIAL_USE_LINFLEX3
if (&SD4 == sdp) {
halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
SPC5_SERIAL_LINFLEX3_START_PCTL);
}
#endif
}
spc5_linflex_init(sdp, config);
@ -417,6 +579,20 @@ void sd_lld_stop(SerialDriver *sdp) {
SPC5_SERIAL_LINFLEX1_STOP_PCTL);
return;
}
#endif
#if SPC5_SERIAL_USE_LINFLEX2
if (&SD3 == sdp) {
halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
SPC5_SERIAL_LINFLEX2_STOP_PCTL);
return;
}
#endif
#if SPC5_SERIAL_USE_LINFLEX3
if (&SD4 == sdp) {
halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
SPC5_SERIAL_LINFLEX3_STOP_PCTL);
return;
}
#endif
}
}

134
os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h
View File

@ -27,62 +27,12 @@
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
#include "spc5_linflex.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name LINIER register bits definitions
* @{
*/
#define SPC5_LINIER_HRIE (1U << 0)
#define SPC5_LINIER_DTIE (1U << 1)
#define SPC5_LINIER_DRIE (1U << 2)
#define SPC5_LINIER_DBEIE (1U << 3)
#define SPC5_LINIER_DBFIE (1U << 4)
#define SPC5_LINIER_WUIE (1U << 5)
#define SPC5_LINIER_LSIE (1U << 6)
#define SPC5_LINIER_BOIE (1U << 7)
#define SPC5_LINIER_FEIE (1U << 8)
#define SPC5_LINIER_HEIE (1U << 11)
#define SPC5_LINIER_CEIE (1U << 12)
#define SPC5_LINIER_BEIE (1U << 13)
#define SPC5_LINIER_OCIE (1U << 14)
#define SPC5_LINIER_SZIE (1U << 15)
/** @} */
/**
* @name UARTSR register bits definitions
* @{
*/
#define SPC5_UARTSR_NF (1U << 0)
#define SPC5_UARTSR_DTF (1U << 1)
#define SPC5_UARTSR_DRF (1U << 2)
#define SPC5_UARTSR_WUF (1U << 5)
#define SPC5_UARTSR_RPS (1U << 6)
#define SPC5_UARTSR_BOF (1U << 7)
#define SPC5_UARTSR_FEF (1U << 8)
#define SPC5_UARTSR_RMB (1U << 9)
#define SPC5_UARTSR_PE0 (1U << 10)
#define SPC5_UARTSR_PE1 (1U << 11)
#define SPC5_UARTSR_PE2 (1U << 12)
#define SPC5_UARTSR_PE3 (1U << 13)
#define SPC5_UARTSR_OCF (1U << 14)
#define SPC5_UARTSR_SZF (1U << 15)
/** @} */
/**
* @name UARTCR register bits definitions
* @{
*/
#define SPC5_UARTCR_UART (1U << 0)
#define SPC5_UARTCR_WL (1U << 1)
#define SPC5_UARTCR_PCE (1U << 2)
#define SPC5_UARTCR_OP (1U << 3)
#define SPC5_UARTCR_TXEN (1U << 4)
#define SPC5_UARTCR_RXEN (1U << 5)
/** @} */
/**
* @name Serial driver allowable modes
* @{
@ -104,7 +54,7 @@
* @details If set to @p TRUE the support for LINFlex-0 is included.
*/
#if !defined(SPC5_SERIAL_USE_LINFLEX0) || defined(__DOXYGEN__)
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
#define SPC5_SERIAL_USE_LINFLEX0 FALSE
#endif
/**
@ -112,7 +62,23 @@
* @details If set to @p TRUE the support for LINFlex-1 is included.
*/
#if !defined(SPC5_SERIAL_USE_LINFLEX1) || defined(__DOXYGEN__)
#define SPC5_SERIAL_USE_LINFLEX1 TRUE
#define SPC5_SERIAL_USE_LINFLEX1 FALSE
#endif
/**
* @brief LINFlex-2 driver enable switch.
* @details If set to @p TRUE the support for LINFlex-2 is included.
*/
#if !defined(SPC5_SERIAL_USE_LINFLEX2) || defined(__DOXYGEN__)
#define SPC5_SERIAL_USE_LINFLEX2 FALSE
#endif
/**
* @brief LINFlex-3 driver enable switch.
* @details If set to @p TRUE the support for LINFlex-3 is included.
*/
#if !defined(SPC5_SERIAL_USE_LINFLEX3) || defined(__DOXYGEN__)
#define SPC5_SERIAL_USE_LINFLEX3 FALSE
#endif
/**
@ -129,6 +95,20 @@
#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
#endif
/**
* @brief LINFlex-2 interrupt priority level setting.
*/
#if !defined(SPC5_SERIAL_LINFLEX2_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_SERIAL_LINFLEX2_PRIORITY 8
#endif
/**
* @brief LINFlex-3 interrupt priority level setting.
*/
#if !defined(SPC5_SERIAL_LINFLEX3_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_SERIAL_LINFLEX3_PRIORITY 8
#endif
/**
* @brief LINFlex-0 peripheral configuration when started.
* @note The default configuration is 1 (always run) in run mode and
@ -173,6 +153,50 @@
SPC5_ME_PCTL_LP(0))
#endif
/**
* @brief LINFlex-2 peripheral configuration when started.
* @note The default configuration is 1 (always run) in run mode and
* 2 (only halt) in low power mode. The defaults of the run modes
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_SERIAL_LINFLEX2_START_PCTL) || defined(__DOXYGEN__)
#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#endif
/**
* @brief LINFlex-2 peripheral configuration when stopped.
* @note The default configuration is 0 (never run) in run mode and
* 0 (never run) in low power mode. The defaults of the run modes
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_SERIAL_LINFLEX2_STOP_PCTL) || defined(__DOXYGEN__)
#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#endif
/**
* @brief LINFlex-3 peripheral configuration when started.
* @note The default configuration is 1 (always run) in run mode and
* 2 (only halt) in low power mode. The defaults of the run modes
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_SERIAL_LINFLEX3_START_PCTL) || defined(__DOXYGEN__)
#define SPC5_SERIAL_LINFLEX3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#endif
/**
* @brief LINFlex-3 peripheral configuration when stopped.
* @note The default configuration is 0 (never run) in run mode and
* 0 (never run) in low power mode. The defaults of the run modes
* are defined in @p hal_lld.h.
*/
#if !defined(SPC5_SERIAL_LINFLEX3_STOP_PCTL) || defined(__DOXYGEN__)
#define SPC5_SERIAL_LINFLEX3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -238,7 +262,7 @@ typedef struct {
uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the volatile LINFlex registers block.*/ \
volatile struct LINFLEX_tag *linflexp;
volatile struct spc5_linflex *linflexp;
/*===========================================================================*/
/* Driver macros. */

510
os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h Normal file
View File

@ -0,0 +1,510 @@
/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPC5xx/spc5_linflex.h
* @brief LINFlex helper driver header.
*
* @addtogroup SPC5xx_LINFLEX
* @{
*/
#ifndef _SPC5_LINFLEX_H_
#define _SPC5_LINFLEX_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name LINIER register bits definitions
* @{
*/
#define SPC5_LINIER_HRIE (1U << 0)
#define SPC5_LINIER_DTIE (1U << 1)
#define SPC5_LINIER_DRIE (1U << 2)
#define SPC5_LINIER_DBEIE (1U << 3)
#define SPC5_LINIER_DBFIE (1U << 4)
#define SPC5_LINIER_WUIE (1U << 5)
#define SPC5_LINIER_LSIE (1U << 6)
#define SPC5_LINIER_BOIE (1U << 7)
#define SPC5_LINIER_FEIE (1U << 8)
#define SPC5_LINIER_HEIE (1U << 11)
#define SPC5_LINIER_CEIE (1U << 12)
#define SPC5_LINIER_BEIE (1U << 13)
#define SPC5_LINIER_OCIE (1U << 14)
#define SPC5_LINIER_SZIE (1U << 15)
/** @} */
/**
* @name UARTSR register bits definitions
* @{
*/
#define SPC5_UARTSR_NF (1U << 0)
#define SPC5_UARTSR_DTF (1U << 1)
#define SPC5_UARTSR_DRF (1U << 2)
#define SPC5_UARTSR_WUF (1U << 5)
#define SPC5_UARTSR_RPS (1U << 6)
#define SPC5_UARTSR_BOF (1U << 7)
#define SPC5_UARTSR_FEF (1U << 8)
#define SPC5_UARTSR_RMB (1U << 9)
#define SPC5_UARTSR_PE0 (1U << 10)
#define SPC5_UARTSR_PE1 (1U << 11)
#define SPC5_UARTSR_PE2 (1U << 12)
#define SPC5_UARTSR_PE3 (1U << 13)
#define SPC5_UARTSR_OCF (1U << 14)
#define SPC5_UARTSR_SZF (1U << 15)
/** @} */
/**
* @name UARTCR register bits definitions
* @{
*/
#define SPC5_UARTCR_UART (1U << 0)
#define SPC5_UARTCR_WL (1U << 1)
#define SPC5_UARTCR_PCE (1U << 2)
#define SPC5_UARTCR_OP (1U << 3)
#define SPC5_UARTCR_TXEN (1U << 4)
#define SPC5_UARTCR_RXEN (1U << 5)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
struct spc5_linflex {
int16_t LINFLEX_reserved1;
union {
vuint16_t R;
struct {
vuint16_t CCD :1;
vuint16_t CFD :1;
vuint16_t LASE :1;
vuint16_t AWUM :1;
vuint16_t MBL :4;
vuint16_t BF :1;
vuint16_t SFTM :1;
vuint16_t LBKM :1;
vuint16_t MME :1;
vuint16_t SBDT :1;
vuint16_t RBLM :1;
vuint16_t SLEEP :1;
vuint16_t INIT :1;
} B;
} LINCR1;
int16_t LINFLEX_reserved2;
union {
vuint16_t R;
struct {
vuint16_t SZIE :1;
vuint16_t OCIE :1;
vuint16_t BEIE :1;
vuint16_t CEIE :1;
vuint16_t HEIE :1;
vuint16_t :2;
vuint16_t FEIE :1;
vuint16_t BOIE :1;
vuint16_t LSIE :1;
vuint16_t WUIE :1;
vuint16_t DBFIE :1;
vuint16_t DBEIE :1;
vuint16_t DRIE :1;
vuint16_t DTIE :1;
vuint16_t HRIE :1;
} B;
} LINIER;
int16_t LINFLEX_reserved3;
union {
vuint16_t R;
struct {
vuint16_t LINS :4;
vuint16_t :2;
vuint16_t RMB :1;
vuint16_t :1;
vuint16_t RBSY :1;
vuint16_t RPS :1;
vuint16_t WUF :1;
vuint16_t DBFF :1;
vuint16_t DBEF :1;
vuint16_t DRF :1;
vuint16_t DTF :1;
vuint16_t HRF :1;
} B;
} LINSR;
int16_t LINFLEX_reserved4;
union {
vuint16_t R;
struct {
vuint16_t SZF :1;
vuint16_t OCF :1;
vuint16_t BEF :1;
vuint16_t CEF :1;
vuint16_t SFEF :1;
vuint16_t BDEF :1;
vuint16_t IDPEF :1;
vuint16_t FEF :1;
vuint16_t BOF :1;
vuint16_t :6;
vuint16_t NF :1;
} B;
} LINESR;
int16_t LINFLEX_reserved5;
union {
vuint16_t R;
struct {
vuint16_t :1;
vuint16_t TDFL :2;
vuint16_t :1;
vuint16_t RDFL :2;
vuint16_t :4;
vuint16_t RXEN :1;
vuint16_t TXEN :1;
vuint16_t OP :1;
vuint16_t PCE :1;
vuint16_t WL :1;
vuint16_t UART :1;
} B;
} UARTCR;
int16_t LINFLEX_reserved6;
union {
vuint16_t R;
struct {
vuint16_t SZF :1;
vuint16_t OCF :1;
vuint16_t PE :4;
vuint16_t RMB :1;
vuint16_t FEF :1;
vuint16_t BOF :1;
vuint16_t RPS :1;
vuint16_t WUF :1;
vuint16_t :2;
vuint16_t DRF :1;
vuint16_t DTF :1;
vuint16_t NF :1;
} B;
} UARTSR;
int16_t LINFLEX_reserved7;
union {
vuint16_t R;
struct {
vuint16_t :5;
vuint16_t LTOM :1;
vuint16_t IOT :1;
vuint16_t TOCE :1;
vuint16_t CNT :8;
} B;
} LINTCSR;
int16_t LINFLEX_reserved8;
union {
vuint16_t R;
struct {
vuint16_t OC2 :8;
vuint16_t OC1 :8;
} B;
} LINOCR;
int16_t LINFLEX_reserved9;
union {
vuint16_t R;
struct {
vuint16_t :4;
vuint16_t RTO :4;
vuint16_t :1;
vuint16_t HTO :7;
} B;
} LINTOCR;
int16_t LINFLEX_reserved10;
union {
vuint16_t R;
struct {
vuint16_t :12;
vuint16_t DIV_F :4;
} B;
} LINFBRR;
int16_t LINFLEX_reserved11;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DIV_M :13;
} B;
} LINIBRR;
int16_t LINFLEX_reserved12;
union {
vuint16_t R;
struct {
vuint16_t :8;
vuint16_t CF :8;
} B;
} LINCFR;
int16_t LINFLEX_reserved13;
union {
vuint16_t R;
struct {
vuint16_t :1;
vuint16_t IOBE :1;
vuint16_t IOPE :1;
vuint16_t WURQ :1;
vuint16_t DDRQ :1;
vuint16_t DTRQ :1;
vuint16_t ABRQ :1;
vuint16_t HTRQ :1;
vuint16_t :8;
} B;
} LINCR2;
int16_t LINFLEX_reserved14;
union {
vuint16_t R;
struct {
vuint16_t DFL :6;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} BIDR;
union {
vuint32_t R;
struct {
vuint32_t DATA3 :8;
vuint32_t DATA2 :8;
vuint32_t DATA1 :8;
vuint32_t DATA0 :8;
} B;
} BDRL;
union {
vuint32_t R;
struct {
vuint32_t DATA7 :8;
vuint32_t DATA6 :8;
vuint32_t DATA5 :8;
vuint32_t DATA4 :8;
} B;
} BDRM;
int16_t LINFLEX_reserved15;
union {
vuint16_t R;
struct {
vuint16_t :8;
vuint16_t FACT :8;
} B;
} IFER;
int16_t LINFLEX_reserved16;
union {
vuint16_t R;
struct {
vuint16_t :12;
vuint16_t IFMI :4;
} B;
} IFMI;
int16_t LINFLEX_reserved17;
union {
vuint16_t R;
struct {
vuint16_t :12;
vuint16_t IFM :4;
} B;
} IFMR;
int16_t LINFLEX_reserved18;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR0;
int16_t LINFLEX_reserved19;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR1;
int16_t LINFLEX_reserved20;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR2;
int16_t LINFLEX_reserved21;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR3;
int16_t LINFLEX_reserved22;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR4;
int16_t LINFLEX_reserved23;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR5;
int16_t LINFLEX_reserved24;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR6;
int16_t LINFLEX_reserved25;
union {
vuint16_t R;
struct {
vuint16_t :3;
vuint16_t DFL :3;
vuint16_t DIR :1;
vuint16_t CCS :1;
vuint16_t :2;
vuint16_t ID :6;
} B;
} IFCR7;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/**
* @name LINFlex units references
* @{
*/
#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE40000UL)
#endif
#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFFE44000UL)
#endif
#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xFFE48000UL)
#endif
#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__)
#define SPC5_LINFLEX3 (*(struct spc5_linflex *)0xFFE4C000UL)
#endif
/** @} */
#endif /* _SPC5_LINFLEX_H_ */
/** @} */