mirror of https://github.com/rusefi/ChibiOS.git
DAC driver *almost* done.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7934 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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@ -186,46 +186,17 @@ typedef enum {
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* @notapi
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* @notapi
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*/
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*/
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#define _dac_isr_full_code(dacp) { \
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#define _dac_isr_full_code(dacp) { \
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if ((dacp)->grpp->circular) { \
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if ((dacp)->grpp->end_cb != NULL) { \
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/* Callback handling.*/ \
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if ((dacp)->depth > 1) { \
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if ((dacp)->grpp->end_cb != NULL) { \
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/* Invokes the callback passing the 2nd half of the buffer.*/ \
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if ((dacp)->depth > 1) { \
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size_t half = (dacp)->depth / 2; \
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/* Invokes the callback passing the 2nd half of the buffer.*/ \
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size_t half_index = half * (dacp)->grpp->num_channels; \
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size_t half = (dacp)->depth / 2; \
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(dacp)->grpp->end_cb(dacp, (dacp)->samples + half_index, half); \
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size_t half_index = half * (dacp)->grpp->num_channels; \
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(dacp)->grpp->end_cb(dacp, (dacp)->samples + half_index, half); \
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} \
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else { \
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/* Invokes the callback passing the whole buffer.*/ \
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(dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth); \
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} \
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} \
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} \
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else { \
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/* End conversion.*/ \
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dac_lld_stop_conversion(dacp); \
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if ((dacp)->grpp->end_cb != NULL) { \
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(dacp)->state = DAC_COMPLETE; \
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if ((dacp)->depth > 1) { \
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/* Invokes the callback passing the 2nd half of the buffer.*/ \
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size_t half = (dacp)->depth / 2; \
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size_t half_index = half * (dacp)->grpp->num_channels; \
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(dacp)->grpp->end_cb(dacp, (dacp)->samples + half_index, half); \
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} \
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else { \
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/* Invokes the callback passing the whole buffer.*/ \
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(dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth); \
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} \
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if ((dacp)->state == DAC_COMPLETE) { \
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(dacp)->state = DAC_READY; \
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(dacp)->grpp = NULL; \
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} \
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} \
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} \
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else { \
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else { \
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(dacp)->state = DAC_READY; \
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/* Invokes the callback passing the whole buffer.*/ \
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(dacp)->grpp = NULL; \
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(dacp)->grpp->end_cb(dacp, (dacp)->samples, (dacp)->depth); \
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} \
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} \
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_dac_wakeup_isr(dacp); \
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} \
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} \
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}
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}
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@ -30,43 +30,53 @@
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/* Driver local definitions. */
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Because ST headers naming inconsistencies.*/
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#if !defined(DAC1)
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#if !defined(DAC1)
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#define DAC1 DAC
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#define DAC1 DAC
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#define rccEnableDAC1 rccEnableDAC
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#define rccDisableDAC1 rccDisableDAC
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#endif
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#endif
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#define DAC_CHN1_DMA_CHANNEL \
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#define DAC1_CH1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC1_CH1_DMA_STREAM, \
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STM32_DAC_CHN1_DMA_CHN)
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STM32_DAC1_CH1_DMA_CHN)
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#define DAC_CHN2_DMA_CHANNEL \
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#define DAC1_CH2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC1_CH2_DMA_STREAM, \
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STM32_DAC_CHN2_DMA_CHN)
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STM32_DAC1_CH2_DMA_CHN)
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#define DAC_CHN3_DMA_CHANNEL \
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#define DAC2_CH1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM, \
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STM32_DMA_GETCHANNEL(STM32_DAC2_CH1_DMA_STREAM, \
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STM32_DAC_CHN3_DMA_CHN)
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STM32_DAC2_CH1_DMA_CHN)
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#define DAC2_CH2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC2_CH2_DMA_STREAM, \
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STM32_DAC2_CH2_DMA_CHN)
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#define CHANNEL_DATA_OFFSET 12
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/** @brief CHN1 driver identifier.*/
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/** @brief DAC1 CH1 driver identifier.*/
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#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__)
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#if STM32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__)
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DACDriver DACD1;
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DACDriver DACD1;
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#endif
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#endif
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/** @brief CHN2 driver identifier.*/
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/** @brief DAC1 CH2 driver identifier.*/
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#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__)
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#if (STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
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DACDriver DACD2;
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DACDriver DACD2;
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#endif
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#endif
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/** @brief CHN3 driver identifier.*/
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/** @brief DAC2 CH1 driver identifier.*/
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#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__)
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#if STM32_DAC_USE_DAC2_CH1 || defined(__DOXYGEN__)
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DACDriver DACD3;
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DACDriver DACD3;
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#endif
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#endif
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/** @brief DAC2 CH2 driver identifier.*/
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#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
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DACDriver DACD4;
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -83,26 +93,20 @@ DACDriver DACD3;
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*/
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*/
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static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
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static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
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#if defined(STM32_DAC_DMA_ERROR_HOOK)
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(void)dacp;
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA errors handling.*/
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/* DMA errors handling.*/
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//~ _dac_isr_error_code(dacp, flags);
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_dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
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}
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}
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else {
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else {
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if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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/* Half transfer processing.*/
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//~ _dac_isr_half_code(dacp);
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_dac_isr_half_code(dacp);
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}
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}
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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/* Transfer complete processing.*/
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//~ _dac_isr_full_code(dacp);
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_dac_isr_full_code(dacp);
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}
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}
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}
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}
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#else
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(void)dacp;
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(void)flags;
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#endif
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}
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}
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/*===========================================================================*/
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/*===========================================================================*/
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@ -120,46 +124,56 @@ static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
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*/
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*/
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void dac_lld_init(void) {
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void dac_lld_init(void) {
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#if STM32_DAC_USE_CHN1
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#if STM32_DAC_USE_DAC1_CH1
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dacObjectInit(&DACD1);
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dacObjectInit(&DACD1);
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DACD1.dac = DAC1;
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DACD1.dac = DAC1;
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DACD1.tim = STM32_TIM6;
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DACD1.dma = STM32_DMA_STREAM(STM32_DAC1_CH1_DMA_STREAM);
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DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY;
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DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
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DACD1.dma = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM);
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STM32_DMA_CR_PL(STM32_DAC1_CH1_DMA_PRIORITY) |
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DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) | \
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) | \
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P | \
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | \
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_TEIE | \
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
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#endif
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#endif
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#if STM32_DAC_USE_CHN2
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#if STM32_DAC_USE_DAC1_CH2
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dacObjectInit(&DACD2);
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dacObjectInit(&DACD2);
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DACD2.dac = DAC1;
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DACD2.dac = DAC1;
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DACD2.tim = STM32_TIM7;
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DACD2.dma = STM32_DMA_STREAM(STM32_DAC1_CH2_DMA_STREAM);
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DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY;
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DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
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DACD2.dma = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM);
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STM32_DMA_CR_PL(STM32_DAC1_CH2_DMA_PRIORITY) |
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DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) | \
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P | \
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | \
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_TEIE | \
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
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#endif
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#endif
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#if STM32_DAC_USE_CHN3
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#if STM32_DAC_USE_DAC2_CH1
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dacObjectInit(&DACD3);
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dacObjectInit(&DACD3);
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DACD3.dac = DAC2;
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DACD3.dac = DAC2;
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DACD3.tim = STM32_TIM18;
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DACD3.dma = STM32_DMA_STREAM(STM32_DAC2_CH1_DMA_STREAM);
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DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY;
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DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
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DACD3.dma = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM);
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STM32_DMA_CR_PL(STM32_DAC2_CH1_DMA_PRIORITY) |
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DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) | \
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P | \
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | \
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_TEIE | \
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
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#endif
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#if STM32_DAC_USE_DAC2_CH2
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dacObjectInit(&DACD4);
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DACD4.dac = DAC2;
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DACD4.dma = STM32_DMA_STREAM(STM32_DAC2_CH2_DMA_STREAM);
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DACD4.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_CIRC |
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STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
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STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE;
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#endif
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#endif
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}
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}
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@ -171,93 +185,110 @@ void dac_lld_init(void) {
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* @notapi
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* @notapi
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*/
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*/
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void dac_lld_start(DACDriver *dacp) {
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void dac_lld_start(DACDriver *dacp) {
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uint32_t arr, regshift, trgo, dataoffset;
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uint32_t cr, regshift, dataoffset;
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bool b;
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bool b;
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/* If in stopped state then enables the DAC and DMA clocks.*/
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if (dacp->state == DAC_STOP) {
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#if STM32_DAC_USE_DAC1_CH1
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#if STM32_DAC_USE_CHN1
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if (&DACD1 == dacp) {
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if (&DACD1 == dacp) {
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rccEnableDAC1(FALSE);
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if (dacp->state == DAC_STOP) {
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/* DAC1 CR data is at bits 0:15 */
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b = dmaStreamAllocate(dacp->dma, STM32_DAC1_CH1_IRQ_PRIORITY,
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regshift = 0;
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC1(false);
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}
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/* Channel-specific parameters.*/
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dataoffset = 0;
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dataoffset = 0;
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/* Timer setup */
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regshift = 0;
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rccEnableTIM6(FALSE);
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}
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rccResetTIM6();
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trgo = STM32_DAC_CR_TSEL_TIM6;
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}
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#endif
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#endif
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#if STM32_DAC_USE_CHN2
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#if STM32_DAC_USE_DAC1_CH2
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if (&DACD2 == dacp) {
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if (&DACD2 == dacp) {
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rccEnableDAC1(FALSE);
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if (dacp->state == DAC_STOP) {
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/* DAC2 CR data is at bits 16:31 */
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b = dmaStreamAllocate(dacp->dma, STM32_DAC1_CH2_IRQ_PRIORITY,
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC1(false);
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}
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/* Channel-specific parameters.*/
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dataoffset = CHANNEL_DATA_OFFSET;
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regshift = 16;
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regshift = 16;
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dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1;
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/* Timer setup */
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rccEnableTIM7(FALSE);
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rccResetTIM7();
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trgo = STM32_DAC_CR_TSEL_TIM7;
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}
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}
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#endif
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#endif
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#if STM32_DAC_USE_CHN3
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#if STM32_DAC_USE_DAC2_CH1
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if (&DACD3 == dacp) {
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if (&DACD3 == dacp) {
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rccEnableDAC2(FALSE);
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if (dacp->state == DAC_STOP) {
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/* DAC3 CR data is at bits 0:15 */
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b = dmaStreamAllocate(dacp->dma, STM32_DAC2_CH1_IRQ_PRIORITY,
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regshift = 0;
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(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableDAC2(false);
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}
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/* Channel-specific parameters.*/
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dataoffset = 0;
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dataoffset = 0;
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/* Timer setup */
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regshift = 0;
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rccEnableTIM18(FALSE);
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rccResetTIM18();
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trgo = STM32_DAC_CR_TSEL_TIM18;
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}
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}
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#endif
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#endif
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#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3
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dacp->clock = STM32_TIMCLK1;
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arr = (dacp->clock / dacp->config->frequency);
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osalDbgAssert((arr <= 0xFFFF),
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"invalid frequency");
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/* Timer configuration.*/
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#if STM32_DAC_USE_DAC2_CH2
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dacp->tim->CR1 = 0; /* Initially stopped. */
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if (&DACD3 == dacp) {
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dacp->tim->PSC = 0; /* Prescaler value. */
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if (dacp->state == DAC_STOP) {
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dacp->tim->DIER = 0;
|
b = dmaStreamAllocate(dacp->dma, STM32_DAC2_CH2_IRQ_PRIORITY,
|
||||||
dacp->tim->ARR = arr;
|
(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
|
||||||
dacp->tim->EGR = TIM_EGR_UG; /* Update event. */
|
(void *)dacp);
|
||||||
dacp->tim->CR2 &= (uint16_t)~TIM_CR2_MMS;
|
osalDbgAssert(!b, "stream already allocated");
|
||||||
dacp->tim->CR2 |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */
|
rccEnableDAC2(false);
|
||||||
dacp->tim->CNT = 0; /* Reset counter. */
|
}
|
||||||
dacp->tim->SR = 0; /* Clear pending IRQs. */
|
|
||||||
/* Update Event IRQ enabled. */
|
|
||||||
/* Timer start.*/
|
|
||||||
dacp->tim->CR1 = TIM_CR1_CEN;
|
|
||||||
|
|
||||||
/* DAC configuration */
|
/* Channel-specific parameters.*/
|
||||||
dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \
|
dataoffset = CHANNEL_DATA_OFFSET;
|
||||||
(STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift;
|
regshift = 16;
|
||||||
|
}
|
||||||
/* DMA setup. */
|
#endif
|
||||||
b = dmaStreamAllocate(dacp->dma,
|
|
||||||
dacp->irqprio,
|
/* DAC configuration.*/
|
||||||
(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
|
#if STM32_DAC_DUAL_MODE == FALSE
|
||||||
(void *)dacp);
|
cr = DAC_CR_DMAEN1 | (dacp->config->cr_tsel << 3) |
|
||||||
osalDbgAssert(!b, "stream already allocated");
|
DAC_CR_TEN1 | DAC_CR_EN1;
|
||||||
switch (dacp->config->dhrm) {
|
dacp->dac->CR = (dacp->dac->CR & ~(0x0000FFFF << regshift)) |
|
||||||
/* Sets the DAC data register */
|
(cr << regshift);
|
||||||
case DAC_DHRM_12BIT_RIGHT:
|
#else
|
||||||
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
|
/* TODO: Dual.*/
|
||||||
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
#endif
|
||||||
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
|
||||||
break;
|
#if STM32_DAC_DUAL_MODE == FALSE
|
||||||
case DAC_DHRM_12BIT_LEFT:
|
switch (dacp->config->dhrm) {
|
||||||
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
|
/* Sets the DAC data register */
|
||||||
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
case DAC_DHRM_12BIT_RIGHT:
|
||||||
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
|
||||||
break;
|
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK)|
|
||||||
case DAC_DHRM_8BIT_RIGHT:
|
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
||||||
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
|
*(&dacp->dac->DHR12R1 + dataoffset) = (uint32_t)dacp->config->sample;
|
||||||
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
|
break;
|
||||||
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
|
case DAC_DHRM_12BIT_LEFT:
|
||||||
break;
|
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
|
||||||
|
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK)|
|
||||||
|
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
|
||||||
|
*(&dacp->dac->DHR12L1 + dataoffset) = (uint32_t)dacp->config->sample;
|
||||||
|
break;
|
||||||
|
case DAC_DHRM_8BIT_RIGHT:
|
||||||
|
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
|
||||||
|
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK)|
|
||||||
|
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
|
||||||
|
*(&dacp->dac->DHR8R1 + dataoffset) = (uint32_t)dacp->config->sample;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
chDbgAssert(false, "unexpected DAC mode");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#else
|
||||||
#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
|
#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
|
||||||
case DAC_DHRM_12BIT_RIGHT_DUAL:
|
case DAC_DHRM_12BIT_RIGHT_DUAL:
|
||||||
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
|
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
|
||||||
|
@ -275,11 +306,7 @@ void dac_lld_start(DACDriver *dacp) {
|
||||||
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
|
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
}
|
|
||||||
|
|
||||||
dacp->dac->CR |= trgo << regshift; /* Enable timer trigger */
|
|
||||||
#endif
|
#endif
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -294,54 +321,65 @@ void dac_lld_stop(DACDriver *dacp) {
|
||||||
/* If in ready state then disables the DAC clock.*/
|
/* If in ready state then disables the DAC clock.*/
|
||||||
if (dacp->state == DAC_READY) {
|
if (dacp->state == DAC_READY) {
|
||||||
|
|
||||||
/* DMA disable.*/
|
/* DMA channel released.*/
|
||||||
dmaStreamRelease(dacp->dma);
|
dmaStreamRelease(dacp->dma);
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN1
|
#if STM32_DAC_USE_DAC1_CH1
|
||||||
if (&DACD1 == dacp) {
|
if (&DACD1 == dacp) {
|
||||||
dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/
|
dacp->dac->CR &= ~DAC_CR_EN1;
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#if STM32_DAC_USE_CHN2
|
|
||||||
if (&DACD2 == dacp) {
|
|
||||||
dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#if STM32_DAC_USE_CHN3
|
|
||||||
if (&DACD3 == dacp) {
|
|
||||||
dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/
|
|
||||||
rccDisableDAC2(FALSE); /* DAC Clock disable.*/
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */
|
|
||||||
dacp->state = DAC_STOP;
|
|
||||||
|
|
||||||
if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) {
|
if ((dacp->dac->CR & DAC_CR_EN2) == 0U) {
|
||||||
/* DAC Clock disable only if all channels are off.*/
|
rccDisableDAC1(false);
|
||||||
rccDisableDAC1(FALSE);
|
}
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_DAC_USE_DAC1_CH2
|
||||||
|
if (&DACD2 == dacp) {
|
||||||
|
dacp->dac->CR &= ~DAC_CR_EN2;
|
||||||
|
|
||||||
|
if ((dacp->dac->CR & DAC_CR_EN1) == 0U) {
|
||||||
|
rccDisableDAC1(false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Sends data over the DAC bus.
|
* @brief Starts a DAC conversion.
|
||||||
* @details This asynchronous function starts a transmit operation.
|
* @details Starts an asynchronous conversion operation.
|
||||||
* @post At the end of the operation the configured callback is invoked.
|
|
||||||
*
|
*
|
||||||
* @param[in] dacp pointer to the @p DACDriver object
|
* @param[in] dacp pointer to the @p DACDriver object
|
||||||
* @param[in] n number of words to send
|
|
||||||
* @param[in] txbuf the pointer to the transmit buffer
|
|
||||||
*
|
*
|
||||||
* @notapi
|
* @notapi
|
||||||
*/
|
*/
|
||||||
void dac_lld_start_conversion(DACDriver *dacp) {
|
void dac_lld_start_conversion(DACDriver *dacp) {
|
||||||
osalDbgAssert(dacp->samples,
|
|
||||||
"dacp->samples is NULL pointer");
|
|
||||||
dmaStreamSetMemory0(dacp->dma, dacp->samples);
|
dmaStreamSetMemory0(dacp->dma, dacp->samples);
|
||||||
dmaStreamSetTransactionSize(dacp->dma, dacp->depth);
|
dmaStreamSetTransactionSize(dacp->dma, dacp->depth);
|
||||||
dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN |
|
dmaStreamSetMode(dacp->dma, dacp->dmamode |
|
||||||
STM32_DMA_CR_CIRC);
|
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
|
||||||
|
STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE);
|
||||||
|
dmaStreamEnable(dacp->dma);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stops an ongoing conversion.
|
||||||
|
* @details This function stops the currently ongoing conversion and returns
|
||||||
|
* the driver in the @p DAC_READY state. If there was no conversion
|
||||||
|
* being processed then the function does nothing.
|
||||||
|
*
|
||||||
|
* @param[in] dacp pointer to the @p DACDriver object
|
||||||
|
*
|
||||||
|
* @iclass
|
||||||
|
*/
|
||||||
|
void dac_lld_stop_conversion(DACDriver *dacp) {
|
||||||
|
|
||||||
|
dmaStreamDisable(dacp->dma);
|
||||||
|
}
|
||||||
|
|
||||||
#endif /* HAL_USE_DAC */
|
#endif /* HAL_USE_DAC */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
|
@ -33,43 +33,6 @@
|
||||||
/* Driver constants. */
|
/* Driver constants. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#define STM32_DAC_CR_EN DAC_CR_EN1
|
|
||||||
#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1
|
|
||||||
#define STM32_DAC_CR_TEN DAC_CR_TEN1
|
|
||||||
|
|
||||||
#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE
|
|
||||||
|
|
||||||
#define STM32_DAC_CR_BOFF_ENABLE (uint32_t)0x00000000
|
|
||||||
#define STM32_DAC_CR_BOFF_DISABLE DAC_CR_BOFF1
|
|
||||||
|
|
||||||
#define STM32_DAC_CR_TSEL_NONE (uint32_t)0x00000000
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM2 DAC_CR_TEN1 | DAC_CR_TSEL1_2
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM4 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM5 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM6 DAC_CR_TEN1
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM7 DAC_CR_TEN1 | DAC_CR_TSEL1_1
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM3 DAC_CR_TEN1 | DAC_CR_TSEL1_0
|
|
||||||
#define STM32_DAC_CR_TSEL_TIM18 DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1
|
|
||||||
#define STM32_DAC_CR_TSEL_EXT_IT9 DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2
|
|
||||||
#define STM32_DAC_CR_TSEL_SOFT DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2
|
|
||||||
|
|
||||||
#define STM32_DAC_CR_WAVE_NONE (uint32_t)0x00000000
|
|
||||||
#define STM32_DAC_CR_WAVE_NOISE DAC_CR_WAVE1_0
|
|
||||||
#define STM32_DAC_CR_WAVE_TRIANGLE DAC_CR_WAVE1_1
|
|
||||||
|
|
||||||
#define STM32_DAC_MAMP_1 (uint32_t)0x00000000
|
|
||||||
#define STM32_DAC_MAMP_3 DAC_CR_MAMP1_0
|
|
||||||
#define STM32_DAC_MAMP_7 DAC_CR_MAMP1_1
|
|
||||||
#define STM32_DAC_MAMP_15 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1
|
|
||||||
#define STM32_DAC_MAMP_31 DAC_CR_MAMP1_2
|
|
||||||
#define STM32_DAC_MAMP_63 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2
|
|
||||||
#define STM32_DAC_MAMP_127 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
|
|
||||||
#define STM32_DAC_MAMP_255 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
|
|
||||||
#define STM32_DAC_MAMP_511 DAC_CR_MAMP1_3
|
|
||||||
#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3
|
|
||||||
#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3
|
|
||||||
#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver pre-compile time settings. */
|
/* Driver pre-compile time settings. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
@ -79,122 +42,131 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN1 driver enable switch.
|
* @brief Enables the DAC dual mode.
|
||||||
* @details If set to @p TRUE the support for DAC CHN1 is included.
|
* @note In dual mode DAC second channels cannot be accessed individually.
|
||||||
* @note The default is @p TRUE.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_USE_CHN1) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_USE_CHN1 FALSE
|
#define STM32_DAC_DUAL_MODE FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN2 driver enable switch.
|
* @brief DAC1 CH1 driver enable switch.
|
||||||
* @details If set to @p TRUE the support for DAC CHN2 is included.
|
* @details If set to @p TRUE the support for DAC1 channel 1 is included.
|
||||||
* @note The default is @p TRUE.
|
* @note The default is @p FALSE.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_USE_CHN2) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_USE_CHN2 FALSE
|
#define STM32_DAC_USE_DAC1_CH1 FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN3 driver enable switch.
|
* @brief DAC1 CH2 driver enable switch.
|
||||||
* @details If set to @p TRUE the support for DAC CHN3 is included.
|
* @details If set to @p TRUE the support for DAC1 channel 2 is included.
|
||||||
* @note The default is @p TRUE.
|
* @note The default is @p FALSE.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_USE_CHN3) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_USE_CHN3 FALSE
|
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN1 interrupt priority level setting.
|
* @brief DAC2 CH1 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for DAC2 channel 1 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN1_IRQ_PRIORITY 10
|
#define STM32_DAC_USE_DAC2_CH1 FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN2 interrupt priority level setting.
|
* @brief DAC2 CH2 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for DAC2 channel 2 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN2_IRQ_PRIORITY 10
|
#define STM32_DAC_USE_DAC2_CH2 FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN3 interrupt priority level setting.
|
* @brief DAC1 CH1 interrupt priority level setting.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN3_IRQ_PRIORITY 10
|
#define STM32_DAC1_CH1_IRQ_PRIORITY 10
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN1 DMA priority (0..3|lowest..highest).
|
* @brief DAC1 CH2 interrupt priority level setting.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN1_DMA_PRIORITY 2
|
#define STM32_DAC1_CH2_IRQ_PRIORITY 10
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN2 DMA priority (0..3|lowest..highest).
|
* @brief DAC2 CH1 interrupt priority level setting.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN2_DMA_PRIORITY 2
|
#define STM32_DAC2_CH1_IRQ_PRIORITY 10
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC CHN3 DMA priority (0..3|lowest..highest).
|
* @brief DAC2 CH2 interrupt priority level setting.
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN2_DMA_PRIORITY 2
|
#define STM32_DAC2_CH2_IRQ_PRIORITY 10
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC DMA error hook.
|
* @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_DMA_ERROR_HOOK(dacp) osalSysHalt()
|
#define STM32_DAC1_CH1_DMA_PRIORITY 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DMA stream used for DAC CHN1 TX operations.
|
* @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
|
||||||
* @note This option is only available on platforms with enhanced DMA.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_DAC1_CH2_DMA_PRIORITY 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DMA stream used for DAC CHN2 TX operations.
|
* @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
|
||||||
* @note This option is only available on platforms with enhanced DMA.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
#define STM32_DAC2_CH1_DMA_PRIORITY 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DMA stream used for DAC CHN3 TX operations.
|
* @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
|
||||||
* @note This option is only available on platforms with enhanced DMA.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)
|
#if !defined(STM32_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||||
#define STM32_DAC_CHN3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
#define STM32_DAC2_CH2_DMA_PRIORITY 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Derived constants and error checks. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1
|
#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1
|
||||||
#error "DAC CHN1 not present in the selected device"
|
#error "DAC1 CH1 not present in the selected device"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2
|
#if STM32_DAC_USE_DAC1_CH2 && !STM32_HAS_DAC1_CH2
|
||||||
#error "DAC CHN2 not present in the selected device"
|
#error "DAC1 CH2 not present in the selected device"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3
|
#if STM32_DAC_USE_DAC2_CH1 && !STM32_HAS_DAC2_CH1
|
||||||
#error "DAC CHN3 not present in the selected device"
|
#error "DAC2 CH1 not present in the selected device"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if !STM32_DAC_USE_CHN1 && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3
|
#if STM32_DAC_USE_DAC2_CH2 && !STM32_HAS_DAC2_CH2
|
||||||
|
#error "DAC2 CH2 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2) && STM32_DAC_DUAL_MODE
|
||||||
|
#error "DACx CH2 cannot be used independently in dual mode"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \
|
||||||
|
!STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2
|
||||||
#error "DAC driver activated but no DAC peripheral assigned"
|
#error "DAC driver activated but no DAC peripheral assigned"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -202,32 +174,41 @@
|
||||||
reassign streams to different channels.*/
|
reassign streams to different channels.*/
|
||||||
#if STM32_ADVANCED_DMA
|
#if STM32_ADVANCED_DMA
|
||||||
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
|
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
|
||||||
#if STM32_DAC_USE_CHN1 && !defined(STM32_DAC_CHN1_DMA_STREAM)
|
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC1_CH1_DMA_STREAM)
|
||||||
#error "DAC1 CHN1 DMA stream not defined"
|
#error "DAC1 CH1 DMA stream not defined"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN2 && !defined(STM32_DAC_CHN2_DMA_STREAM)
|
#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC1_CH2_DMA_STREAM)
|
||||||
#error "DAC1 CHN2 DMA stream not defined"
|
#error "DAC1 CH2 DMA stream not defined"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN3 && !defined(STM32_DAC_CHN3_DMA_STREAM)
|
#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC2_CH1_DMA_STREAM)
|
||||||
#error "DAC1 CHN3 DMA stream not defined"
|
#error "DAC2 CH1 DMA stream not defined"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC2_CH2_DMA_STREAM)
|
||||||
|
#error "DAC2 CH2 DMA stream not defined"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Check on the validity of the assigned DMA channels.*/
|
/* Check on the validity of the assigned DMA channels.*/
|
||||||
#if STM32_DAC_USE_CHN1 && \
|
#if STM32_DAC_USE_DAC1_CH1 && \
|
||||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)
|
!STM32_DMA_IS_VALID_ID(STM32_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
|
||||||
#error "invalid DMA stream associated to DAC CHN1"
|
#error "invalid DMA stream associated to DAC1 CH1"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN2 && \
|
#if STM32_DAC_USE_DAC1_CH2 && \
|
||||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)
|
!STM32_DMA_IS_VALID_ID(STM32_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
|
||||||
#error "invalid DMA stream associated to DAC CHN2"
|
#error "invalid DMA stream associated to DAC1 CH2"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN3 && \
|
#if STM32_DAC_USE_DAC2_CH1 && \
|
||||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)
|
!STM32_DMA_IS_VALID_ID(STM32_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
|
||||||
#error "invalid DMA stream associated to DAC CHN3"
|
#error "invalid DMA stream associated to DAC2 CH1"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_DAC_USE_DAC2_CH2 && \
|
||||||
|
!STM32_DMA_IS_VALID_ID(STM32_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
|
||||||
|
#error "invalid DMA stream associated to DAC2 CH2"
|
||||||
#endif
|
#endif
|
||||||
#endif /* STM32_ADVANCED_DMA */
|
#endif /* STM32_ADVANCED_DMA */
|
||||||
|
|
||||||
|
@ -249,19 +230,45 @@ typedef struct DACDriver DACDriver;
|
||||||
*/
|
*/
|
||||||
typedef uint16_t dacsample_t;
|
typedef uint16_t dacsample_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Possible DAC failure causes.
|
||||||
|
* @note Error codes are architecture dependent and should not relied
|
||||||
|
* upon.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||||
|
DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */
|
||||||
|
} dacerror_t;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief DAC notification callback type.
|
* @brief DAC notification callback type.
|
||||||
*
|
*
|
||||||
* @param[in] dacp pointer to the @p DACDriver object triggering the
|
* @param[in] dacp pointer to the @p DACDriver object triggering the
|
||||||
|
* @param[in] buffer pointer to the next semi-buffer to be filled
|
||||||
|
* @param[in] n number of buffer rows available starting from @p buffer
|
||||||
* callback
|
* callback
|
||||||
*/
|
*/
|
||||||
typedef void (*daccallback_t)(DACDriver *dacp);
|
typedef void (*daccallback_t)(DACDriver *dacp,
|
||||||
|
const dacsample_t *buffer,
|
||||||
|
size_t n);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC error callback type.
|
||||||
|
*
|
||||||
|
* @param[in] dacp pointer to the @p DACDriver object triggering the
|
||||||
|
* callback
|
||||||
|
* @param[in] err ADC error code
|
||||||
|
*/
|
||||||
|
typedef void (*dacerrorcallback_t)(DACDriver *adcp, dacerror_t err);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Samples alignment and size mode.
|
||||||
|
*/
|
||||||
typedef enum {
|
typedef enum {
|
||||||
DAC_DHRM_12BIT_RIGHT = 0,
|
DAC_DHRM_12BIT_RIGHT = 0,
|
||||||
DAC_DHRM_12BIT_LEFT = 1,
|
DAC_DHRM_12BIT_LEFT = 1,
|
||||||
DAC_DHRM_8BIT_RIGHT = 2,
|
DAC_DHRM_8BIT_RIGHT = 2,
|
||||||
#if STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)
|
#if STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
|
||||||
DAC_DHRM_12BIT_RIGHT_DUAL = 3,
|
DAC_DHRM_12BIT_RIGHT_DUAL = 3,
|
||||||
DAC_DHRM_12BIT_LEFT_DUAL = 4,
|
DAC_DHRM_12BIT_LEFT_DUAL = 4,
|
||||||
DAC_DHRM_8BIT_RIGHT_DUAL = 5
|
DAC_DHRM_8BIT_RIGHT_DUAL = 5
|
||||||
|
@ -273,18 +280,18 @@ typedef enum {
|
||||||
*/
|
*/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
/**
|
/**
|
||||||
* @brief Number of DAC channels.
|
* @brief Number of DAC channels.
|
||||||
*/
|
*/
|
||||||
uint32_t num_channels;
|
uint32_t num_channels;
|
||||||
/**
|
/**
|
||||||
* @brief Operation complete callback or @p NULL.
|
* @brief Operation complete callback or @p NULL.
|
||||||
*/
|
*/
|
||||||
daccallback_t end_cb;
|
daccallback_t end_cb;
|
||||||
/**
|
/**
|
||||||
* @brief Error handling callback or @p NULL.
|
* @brief Error handling callback or @p NULL.
|
||||||
*/
|
*/
|
||||||
daccallback_t error_cb;
|
dacerrorcallback_t error_cb;
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
} DACConversionGroup;
|
} DACConversionGroup;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -292,18 +299,21 @@ typedef struct {
|
||||||
*/
|
*/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
/**
|
/**
|
||||||
* @brief Timer frequency in Hz.
|
* @brief Initial sample to be presented on outputs.
|
||||||
*/
|
*/
|
||||||
uint32_t frequency;
|
dacsample_t sample;
|
||||||
/* End of the mandatory fields.*/
|
/* End of the mandatory fields.*/
|
||||||
/**
|
/**
|
||||||
* @brief DAC data holding register mode.
|
* @brief DAC data holding register mode.
|
||||||
*/
|
*/
|
||||||
dacdhrmode_t dhrm;
|
dacdhrmode_t dhrm;
|
||||||
/**
|
/**
|
||||||
* @brief DAC initialization data.
|
* @brief DAC initialization data.
|
||||||
|
* @note This field contains the (not shifted) value to be put into the
|
||||||
|
* TSEL field of the DAC CR register during initialization. All
|
||||||
|
* other fields are handled internally.
|
||||||
*/
|
*/
|
||||||
uint32_t cr_flags;
|
uint32_t cr_tsel;
|
||||||
} DACConfig;
|
} DACConfig;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -311,34 +321,34 @@ typedef struct {
|
||||||
*/
|
*/
|
||||||
struct DACDriver {
|
struct DACDriver {
|
||||||
/**
|
/**
|
||||||
* @brief Driver state.
|
* @brief Driver state.
|
||||||
*/
|
*/
|
||||||
dacstate_t state;
|
dacstate_t state;
|
||||||
/**
|
/**
|
||||||
* @brief Conversion group.
|
* @brief Conversion group.
|
||||||
*/
|
*/
|
||||||
const DACConversionGroup *grpp;
|
const DACConversionGroup *grpp;
|
||||||
/**
|
/**
|
||||||
* @brief Samples buffer pointer.
|
* @brief Samples buffer pointer.
|
||||||
*/
|
*/
|
||||||
const dacsample_t *samples;
|
const dacsample_t *samples;
|
||||||
/**
|
/**
|
||||||
* @brief Samples buffer size.
|
* @brief Samples buffer size.
|
||||||
*/
|
*/
|
||||||
uint16_t depth;
|
uint16_t depth;
|
||||||
/**
|
/**
|
||||||
* @brief Current configuration data.
|
* @brief Current configuration data.
|
||||||
*/
|
*/
|
||||||
const DACConfig *config;
|
const DACConfig *config;
|
||||||
#if DAC_USE_WAIT || defined(__DOXYGEN__)
|
#if DAC_USE_WAIT || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief Waiting thread.
|
* @brief Waiting thread.
|
||||||
*/
|
*/
|
||||||
thread_reference_t thread;
|
thread_reference_t thread;
|
||||||
#endif /* DAC_USE_WAIT */
|
#endif /* DAC_USE_WAIT */
|
||||||
#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief Mutex protecting the bus.
|
* @brief Mutex protecting the bus.
|
||||||
*/
|
*/
|
||||||
mutex_t mutex;
|
mutex_t mutex;
|
||||||
#endif /* DAC_USE_MUTUAL_EXCLUSION */
|
#endif /* DAC_USE_MUTUAL_EXCLUSION */
|
||||||
|
@ -347,29 +357,17 @@ struct DACDriver {
|
||||||
#endif
|
#endif
|
||||||
/* End of the mandatory fields.*/
|
/* End of the mandatory fields.*/
|
||||||
/**
|
/**
|
||||||
* @brief Pointer to the DAC registers block.
|
* @brief Pointer to the DAC registers block.
|
||||||
*/
|
*/
|
||||||
DAC_TypeDef *dac;
|
DAC_TypeDef *dac;
|
||||||
/**
|
/**
|
||||||
* @brief Pointer to the TIMx registers block.
|
* @brief Transmit DMA stream.
|
||||||
*/
|
|
||||||
stm32_tim_t *tim;
|
|
||||||
/**
|
|
||||||
* @brief The Timer IRQ priority.
|
|
||||||
*/
|
|
||||||
uint32_t irqprio;
|
|
||||||
/**
|
|
||||||
* @brief Transmit DMA stream.
|
|
||||||
*/
|
*/
|
||||||
const stm32_dma_stream_t *dma;
|
const stm32_dma_stream_t *dma;
|
||||||
/**
|
/**
|
||||||
* @brief TX DMA mode bit mask.
|
* @brief TX DMA mode bit mask.
|
||||||
*/
|
*/
|
||||||
uint32_t dmamode;
|
uint32_t dmamode;
|
||||||
/**
|
|
||||||
* @brief Timer base clock.
|
|
||||||
*/
|
|
||||||
uint32_t clock;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
@ -380,18 +378,22 @@ struct DACDriver {
|
||||||
/* External declarations. */
|
/* External declarations. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)
|
#if STM32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
|
||||||
extern DACDriver DACD1;
|
extern DACDriver DACD1;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)
|
#if STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
|
||||||
extern DACDriver DACD2;
|
extern DACDriver DACD2;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)
|
#if STM32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__)
|
||||||
extern DACDriver DACD3;
|
extern DACDriver DACD3;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
|
||||||
|
extern DACDriver DACD4;
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -331,6 +331,37 @@
|
||||||
#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
|
#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name DAC peripheral specific RCC operations
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Enables the DAC1 peripheral clock.
|
||||||
|
*
|
||||||
|
* @param[in] lp low power enable flag
|
||||||
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define rccEnableDAC1(lp) rccEnableAPB2(RCC_APB1ENR_DACEN, lp)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables the DAC1 peripheral clock.
|
||||||
|
*
|
||||||
|
* @param[in] lp low power enable flag
|
||||||
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define rccDisableDAC1(lp) rccDisableAPB2(RCC_APB1ENR_DACEN, lp)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Resets the DAC1 peripheral.
|
||||||
|
*
|
||||||
|
* @api
|
||||||
|
*/
|
||||||
|
#define rccResetDAC1() rccResetAPB2(RCC_APB1RSTR_DACRST)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name DMA peripheral specific RCC operations
|
* @name DMA peripheral specific RCC operations
|
||||||
* @{
|
* @{
|
||||||
|
|
|
@ -366,8 +366,16 @@
|
||||||
#define STM32_CAN_MAX_FILTERS 28
|
#define STM32_CAN_MAX_FILTERS 28
|
||||||
|
|
||||||
/* DAC attributes.*/
|
/* DAC attributes.*/
|
||||||
#define STM32_HAS_DAC1 FALSE
|
#define STM32_HAS_DAC1_CH1 TRUE
|
||||||
#define STM32_HAS_DAC2 FALSE
|
#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||||
|
#define STM32_DAC1_CH1_DMA_CHN 0x00700000
|
||||||
|
|
||||||
|
#define STM32_HAS_DAC1_CH2 TRUE
|
||||||
|
#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||||
|
#define STM32_DAC1_CH2_DMA_CHN 0x07000000
|
||||||
|
|
||||||
|
#define STM32_HAS_DAC2_CH1 FALSE
|
||||||
|
#define STM32_HAS_DAC2_CH2 FALSE
|
||||||
|
|
||||||
/* DMA attributes.*/
|
/* DMA attributes.*/
|
||||||
#define STM32_ADVANCED_DMA TRUE
|
#define STM32_ADVANCED_DMA TRUE
|
||||||
|
|
|
@ -0,0 +1,52 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
|
||||||
|
<stringAttribute key="bad_container_name" value="\STM32F4xx-DAC\debug"/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="CR2-adc-adcp-adc_lld_start_conversion-(format)" val="4"/><content id="CR2-adc-null-port_wait_for_interrupt-(format)" val="4"/><content id="cr2-adc_lld_start_conversion-(format)" val="4"/></contentList>"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32F4xx-DAC"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.865376734"/>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||||
|
<listEntry value="/STM32F4xx-DAC"/>
|
||||||
|
</listAttribute>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||||
|
<listEntry value="4"/>
|
||||||
|
</listAttribute>
|
||||||
|
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
|
||||||
|
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
|
||||||
|
</listAttribute>
|
||||||
|
</launchConfiguration>
|
|
@ -93,15 +93,15 @@
|
||||||
/*
|
/*
|
||||||
* DAC driver system settings.
|
* DAC driver system settings.
|
||||||
*/
|
*/
|
||||||
#define STM32_DAC_USE_CHN1 TRUE
|
#define STM32_DAC_DUAL_MODE FALSE
|
||||||
#define STM32_DAC_USE_CHN2 FALSE
|
#define STM32_DAC_USE_DAC1_CH1 TRUE
|
||||||
#define STM32_DAC_CHN1_IRQ_PRIORITY 10
|
#define STM32_DAC_USE_DAC1_CH2 TRUE
|
||||||
#define STM32_DAC_CHN2_IRQ_PRIORITY 10
|
#define STM32_DAC1_CH1_IRQ_PRIORITY 10
|
||||||
#define STM32_DAC_CHN1_DMA_PRIORITY 2
|
#define STM32_DAC1_CH2_IRQ_PRIORITY 10
|
||||||
#define STM32_DAC_CHN2_DMA_PRIORITY 2
|
#define STM32_DAC1_CH1_DMA_PRIORITY 2
|
||||||
#define STM32_DAC_DMA_ERROR_HOOK(dacp) osalSysHalt()
|
#define STM32_DAC1_CH2_DMA_PRIORITY 2
|
||||||
#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||||
#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
#define STM32_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* EXT driver system settings.
|
* EXT driver system settings.
|
||||||
|
|
Loading…
Reference in New Issue