mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@266 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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2da330780e
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@ -81,11 +81,12 @@ void hwinit(void) {
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* NVIC/SCB initialization.
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*/
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4).
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SCB_SHPR(2) = 0xF0 << 16; // PendSV at lowest priority.
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/*
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* SysTick initialization.
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*/
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SCB_SHPR(2) = 0x80 << 24; // SysTick at priority 8:0.
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SCB_SHPR(2) |= 0x40 << 24; // SysTick at priority 4:0.
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ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
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ST_CVR = 0;
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ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS;
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@ -93,5 +94,5 @@ void hwinit(void) {
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/*
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* Other subsystems initialization.
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*/
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InitSerial(0xA0, 0xA0, 0xA0);
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InitSerial(0x80, 0x80, 0x80);
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}
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@ -23,15 +23,18 @@
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/*
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* System idle thread loop.
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*/
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__attribute__((weak))
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void _IdleThread(void *p) {
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while (TRUE) {
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// asm volatile ("wfi");
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}
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}
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/*
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* System console message (not implemented).
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*/
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__attribute__((weak))
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void chSysPuts(char *msg) {
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}
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@ -39,15 +42,10 @@ void chSysPuts(char *msg) {
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* Context switch.
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*/
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void chSysSwitchI(Thread *otp, Thread *ntp) {
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register struct intctx * volatile sp asm("sp"); /* Don't ask... */
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#ifdef CH_CURRP_REGISTER_CACHE
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asm ("" : : : "r4", "r5", "r6", "r8", "r9", "r10", "r11", "lr");
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#else
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asm ("" : : : "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "lr");
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#endif
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otp->p_ctx.r13 = sp;
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sp = ntp->p_ctx.r13;
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asm volatile ("cpsie i \n\t" \
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"svc #0 \n\t" \
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"cpsid i ");
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}
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/*
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@ -64,10 +62,10 @@ void chSysHalt(void) {
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__attribute__((naked, weak))
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void threadstart(void) {
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chSysUnlock();
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asm volatile ("mov r0, r5 \n\t" \
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"blx r4 \n\t" \
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"bl chThdExit ");
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asm volatile ("cpsie i \n\t" \
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"blx r1 \n\t" \
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"bl chThdExit \n\t" \
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"bl chSysHalt ");
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}
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/*
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@ -93,40 +91,75 @@ void *retaddr;
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void chSysIRQExitI(void) {
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chSysLock();
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if (SCB_ICSR & ICSR_RETTOBASE_MASK) {
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if (chSchRescRequiredI()) {
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asm volatile ("mrs r0, PSP \n\t" \
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"ldr r2, [r0, #24] \n\t" \
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"ldr r1, =retaddr \n\t" \
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"str r2, [r1] \n\t" \
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"ldr r1, =threadswitch \n\t" \
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"str r1, [r0, #24] ");
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return; /* Note, returns *without* re-enabling interrupts.*/
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}
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if ((SCB_ICSR & ICSR_RETTOBASE) && chSchRescRequiredI()) {
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SCB_ICSR = ICSR_PENDSVSET;
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}
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chSysUnlock();
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}
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/*
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* This code is executed in thread mode when exiting from an ISR routine that
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* requires rescheduling.
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* System invoked context switch.
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*/
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__attribute__((naked, weak))
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void threadswitch(void) {
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__attribute__((naked))
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void SVCallVector(Thread *otp, Thread *ntp) {
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asm volatile ("sub sp, sp, #4 \n\t" \
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"push {r0-r3, r12, lr} \n\t" \
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"mrs r0, XPSR \n\t" \
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"push {r0} \n\t" \
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"ldr r0, =retaddr \n\t" \
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"ldr r0, [r0] \n\t" \
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"orr r0, r0, #1 \n\t" \
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"str r0, [sp, #28] \n\t" \
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"bl chSchDoRescheduleI \n\t" \
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"pop {r0} \n\t" \
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"msr XPSR, r0 \n\t" \
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"pop {r0-r3, r12, lr} \n\t" \
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"cpsie i \n\t" \
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"pop {pc} ");
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#ifdef CH_CURRP_REGISTER_CACHE
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asm volatile ("mrs r12, PSP \n\t" \
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"stmdb r12!, {r4-6,r8-r11, lr} \n\t" \
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"str r12, [r0, #16] \n\t" \
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"ldr r12, [r1, #16] \n\t" \
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"ldmia r12!, {r4-6,r8-r11, lr} \n\t" \
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"msr PSP, r12 \n\t" \
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"bx lr ");
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#else
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asm volatile ("mrs r12, PSP \n\t" \
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"stmdb r12!, {r4-r11, lr} \n\t" \
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"str r12, [r0, #16] \n\t" \
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"ldr r12, [r1, #16] \n\t" \
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"ldmia r12!, {r4-r11, lr} \n\t" \
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"msr PSP, r12 \n\t" \
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"bx lr ");
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#endif
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}
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/*
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* Preemption invoked context switch.
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*/
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__attribute__((naked))
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void PendSVVector(void) {
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Thread *otp;
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register struct intctx *sp_thd asm("r12");
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asm volatile ("cpsid i \n\t" \
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"mrs %0, PSP" : "=r" (sp_thd) : );
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#ifdef CH_CURRP_REGISTER_CACHE
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asm volatile ("stmdb %0!, {r4-r6,r8-r11, lr}" :
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"=r" (sp_thd) :
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"r" (sp_thd));
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#else
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asm volatile ("stmdb %0!, {r4-r11, lr}" :
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"=r" (sp_thd) :
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"r" (sp_thd));
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#endif
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(otp = currp)->p_ctx.r13 = sp_thd;
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chSchReadyI(otp);
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(currp = fifo_remove(&rlist.r_queue))->p_state = PRCURR;
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rlist.r_preempt = CH_TIME_QUANTUM;
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#ifdef CH_USE_TRACE
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chDbgTrace(otp, currp);
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#endif
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sp_thd = currp->p_ctx.r13;
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#ifdef CH_CURRP_REGISTER_CACHE
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asm volatile ("ldmia %0!, {r4-r6,r8-r11, lr}" : : "r" (sp_thd));
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#else
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asm volatile ("ldmia %0!, {r4-r11, lr}" : : "r" (sp_thd));
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#endif
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asm volatile ("msr PSP, %0 \n\t" \
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"cpsie i \n\t" \
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"bx lr" : : "r" (sp_thd));
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}
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@ -23,17 +23,9 @@
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typedef void *regarm;
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/*
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* Interrupt saved context.
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* Interrupt saved context, empty in this architecture.
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*/
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struct extctx {
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regarm xpsr;
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regarm r0;
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regarm r1;
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regarm r2;
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regarm r3;
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regarm r12;
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regarm lr;
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regarm pc;
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};
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/*
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@ -50,7 +42,15 @@ struct intctx {
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regarm r9;
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regarm r10;
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regarm r11;
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regarm lr;
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regarm lr_exc;
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regarm r0;
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regarm r1;
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regarm r2;
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regarm r3;
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regarm r12;
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regarm lr_thd;
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regarm pc;
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regarm xpsr;
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};
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/*
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@ -68,15 +68,17 @@ typedef struct {
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tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
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wsize - \
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sizeof(struct intctx)); \
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tp->p_ctx.r13->r4 = pf; \
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tp->p_ctx.r13->r5 = arg; \
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tp->p_ctx.r13->lr = threadstart; \
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tp->p_ctx.r13->r0 = arg; \
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tp->p_ctx.r13->r1 = pf; \
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tp->p_ctx.r13->lr_exc = (regarm)0xFFFFFFFD; \
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tp->p_ctx.r13->pc = threadstart; \
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tp->p_ctx.r13->xpsr = (regarm)0x01000000; \
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}
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#define chSysLock() asm("cpsid i")
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#define chSysUnlock() asm("cpsie i")
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#define INT_REQUIRED_STACK 0x10
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#define INT_REQUIRED_STACK 0
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#define StackAlign(n) ((((n) - 1) | 3) + 1)
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#define UserStackSize(n) StackAlign(sizeof(Thread) + \
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sizeof(struct intctx) + \
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#define chSysIRQEnterI()
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/* It should be 8.*/
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#define IDLE_THREAD_STACK_SIZE 16
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#define IDLE_THREAD_STACK_SIZE 0
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void _IdleThread(void *p) __attribute__((noreturn));
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void chSysHalt(void);
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@ -114,15 +114,15 @@ typedef struct {
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#define SCB_AFSR (SCBBase->AFSR)
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#define ICSR_VECTACTIVE_MASK (0x1FF << 0)
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#define ICSR_RETTOBASE_MASK (0x1 << 11)
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#define ICSR_RETTOBASE (0x1 << 11)
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#define ICSR_VECTPENDING_MASK (0x1FF << 12)
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#define ICSR_ISRPENDING_MASK (0x1 << 22)
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#define ICSR_ISRPREEMPT_MASK (0x1 << 23)
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#define ICSR_PENDSTCLR_MASK (0x1 << 25)
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#define ICSR_PENDSTSET_MASK (0x1 << 26)
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#define ICSR_PENDSVCLR_MASK (0x1 << 27)
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#define ICSR_PENDSVSET_MASK (0x1 << 28)
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#define ICSR_NMIPENDSET_MASK (0x1 << 31)
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#define ICSR_ISRPENDING (0x1 << 22)
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#define ICSR_ISRPREEMPT (0x1 << 23)
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#define ICSR_PENDSTCLR (0x1 << 25)
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#define ICSR_PENDSTSET (0x1 << 26)
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#define ICSR_PENDSVCLR (0x1 << 27)
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#define ICSR_PENDSVSET (0x1 << 28)
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#define ICSR_NMIPENDSET (0x1 << 31)
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#define AIRCR_VECTKEY 0x05FA0000
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#define AIRCR_PRIGROUP_MASK (0x7 << 8)
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