mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3670 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -7,7 +7,7 @@ Compiler: IAR C/C++ Compiler for ARM 6.30.3.33228
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*** ChibiOS/RT test suite
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*** ChibiOS/RT test suite
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***
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***
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*** Kernel: 2.3.5unstable
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*** Kernel: 2.3.5unstable
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*** Compiled: Dec 27 2011 - 15:57:01
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*** Compiled: Dec 28 2011 - 10:01:37
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*** Compiler: IAR
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*** Compiler: IAR
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*** Architecture: ARMv7-ME
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*** Architecture: ARMv7-ME
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*** Core Variant: Cortex-M4
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*** Core Variant: Cortex-M4
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@ -133,7 +133,9 @@ __attribute__((naked))
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#endif
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#endif
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void _port_switch_from_isr(void) {
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void _port_switch_from_isr(void) {
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dbg_check_lock();
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chSchDoReschedule();
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chSchDoReschedule();
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dbg_check_unlock();
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asm volatile ("_port_exit_from_isr:" : : : "memory");
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asm volatile ("_port_exit_from_isr:" : : : "memory");
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#if CORTEX_ALTERNATE_SWITCH
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#if CORTEX_ALTERNATE_SWITCH
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SCB_ICSR = ICSR_PENDSVSET;
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SCB_ICSR = ICSR_PENDSVSET;
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@ -206,6 +206,23 @@ struct intctx {};
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#endif /* defined(__DOXYGEN__) */
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#endif /* defined(__DOXYGEN__) */
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/**
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* @brief Excludes the default @p chSchIsPreemptionRequired()implementation.
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*/
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#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
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#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
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/**
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* @brief Inlineable version of this kernel function.
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*/
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#define chSchIsPreemptionRequired() \
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(rlist.r_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \
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firstprio(&rlist.r_queue) >= currp->p_prio)
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#else /* CH_TIME_QUANTUM == 0 */
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#define chSchIsPreemptionRequired() \
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(firstprio(&rlist.r_queue) > currp->p_prio)
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#endif /* CH_TIME_QUANTUM == 0 */
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#endif /* _FROM_ASM_ */
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#endif /* _FROM_ASM_ */
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#endif /* _CHCORE_H_ */
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#endif /* _CHCORE_H_ */
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@ -103,8 +103,20 @@ void _port_irq_epilogue(regarm_t lr) {
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ctxp = (struct extctx *)__get_PSP();
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ctxp = (struct extctx *)__get_PSP();
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ctxp--;
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ctxp--;
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__set_PSP((unsigned long)ctxp);
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__set_PSP((unsigned long)ctxp);
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ctxp->pc = (regarm_t)_port_switch_from_isr;
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ctxp->xpsr = (regarm_t)0x01000000;
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ctxp->xpsr = (regarm_t)0x01000000;
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/* The exit sequence is different depending on if a preemption is
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required or not.*/
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if (chSchIsPreemptionRequired()) {
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/* Preemption is required we need to enforce a context switch.*/
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ctxp->pc = (regarm_t)_port_switch_from_isr;
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}
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else {
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/* Preemption not required, we just need to exit the exception
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atomically.*/
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ctxp->pc = (regarm_t)_port_exit_from_isr;
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}
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/* Note, returning without unlocking is intentional, this is done in
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/* Note, returning without unlocking is intentional, this is done in
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order to keep the rest of the context switching atomic.*/
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order to keep the rest of the context switching atomic.*/
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}
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}
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@ -352,32 +352,14 @@ struct context {
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}
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}
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#endif
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#endif
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#if 0
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/**
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* @brief Excludes the default @p chSchIsPreemptionRequired()implementation.
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*/
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#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
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#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
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/**
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* @brief Inlineable version of this kernel function.
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*/
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#define chSchIsPreemptionRequired() \
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(rlist.r_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \
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firstprio(&rlist.r_queue) >= currp->p_prio)
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#else /* CH_TIME_QUANTUM == 0 */
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#define chSchIsPreemptionRequired() \
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(firstprio(&rlist.r_queue) > currp->p_prio)
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#endif /* CH_TIME_QUANTUM == 0 */
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#endif
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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#endif
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void port_halt(void);
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void port_halt(void);
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void _port_switch(Thread *ntp, Thread *otp);
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void _port_irq_epilogue(regarm_t lr);
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void _port_irq_epilogue(regarm_t lr);
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void _port_switch_from_isr(void);
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void _port_switch_from_isr(void);
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void _port_exit_from_isr(void);
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void _port_switch(Thread *ntp, Thread *otp);
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void _port_thread_start(void);
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void _port_thread_start(void);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@ -171,7 +171,6 @@ void _port_irq_epilogue(void) {
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else {
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else {
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/* Preemption not required, we just need to exit the exception
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/* Preemption not required, we just need to exit the exception
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atomically.*/
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atomically.*/
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void _port_exit_from_isr(void);
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ctxp->pc = (regarm_t)_port_exit_from_isr;
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ctxp->pc = (regarm_t)_port_exit_from_isr;
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}
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}
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@ -469,31 +469,15 @@ struct context {
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}
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}
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#endif
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#endif
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/**
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* @brief Excludes the default @p chSchIsPreemptionRequired()implementation.
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*/
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#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
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#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
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/**
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* @brief Inlineable version of this kernel function.
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*/
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#define chSchIsPreemptionRequired() \
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(rlist.r_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \
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firstprio(&rlist.r_queue) >= currp->p_prio)
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#else /* CH_TIME_QUANTUM == 0 */
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#define chSchIsPreemptionRequired() \
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(firstprio(&rlist.r_queue) > currp->p_prio)
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#endif /* CH_TIME_QUANTUM == 0 */
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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#endif
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void port_halt(void);
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void port_halt(void);
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void _port_init(void);
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void _port_init(void);
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void _port_switch(Thread *ntp, Thread *otp);
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void _port_irq_epilogue(void);
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void _port_irq_epilogue(void);
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void _port_switch_from_isr(void);
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void _port_switch_from_isr(void);
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void _port_exit_from_isr(void);
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void _port_switch(Thread *ntp, Thread *otp);
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void _port_thread_start(void);
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void _port_thread_start(void);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@ -37,7 +37,6 @@ SCB_ICSR SET 0xE000ED04
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SECTION .text:CODE:NOROOT(2)
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SECTION .text:CODE:NOROOT(2)
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EXTERN chThdExit
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EXTERN chThdExit
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EXTERN chSchIsPreemptionRequired
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EXTERN chSchDoReschedule
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EXTERN chSchDoReschedule
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#if CH_DBG_SYSTEM_STATE_CHECK
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#if CH_DBG_SYSTEM_STATE_CHECK
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EXTERN dbg_check_unlock
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EXTERN dbg_check_unlock
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* Exception handlers return here for context switching.
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* Exception handlers return here for context switching.
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*/
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*/
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PUBLIC _port_switch_from_isr
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PUBLIC _port_switch_from_isr
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PUBLIC _port_exit_from_isr
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_port_switch_from_isr:
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_port_switch_from_isr:
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#if CH_DBG_SYSTEM_STATE_CHECK
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl dbg_check_lock
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bl dbg_check_lock
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#endif
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#endif
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bl chSchIsPreemptionRequired
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cmp r0, #0
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beq noresch
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bl chSchDoReschedule
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bl chSchDoReschedule
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noresch:
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#if CH_DBG_SYSTEM_STATE_CHECK
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl dbg_check_unlock
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bl dbg_check_unlock
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#endif
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#endif
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_port_exit_from_isr:
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ldr r2, =SCB_ICSR
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ldr r2, =SCB_ICSR
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movs r3, #128
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movs r3, #128
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#if CORTEX_ALTERNATE_SWITCH
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#if CORTEX_ALTERNATE_SWITCH
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