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Added support for STM32H7A3/B3/A3Q/B3Q and demo for Nucleo144 STM32H7A3-Q. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15607 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-04-25 11:36:36 +00:00
parent 6ead2432cf
commit f6bd51f33e
5 changed files with 37 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
demos/STM32/RT-STM32H7A3ZI_Q-NUCLEO144/cfg/mcuconf.h
View File

@ -88,8 +88,8 @@
#define STM32_PLL1_DIVN_VALUE 260 #define STM32_PLL1_DIVN_VALUE 260
#define STM32_PLL1_FRACN_VALUE 0 #define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL1_DIVP_VALUE 1 #define STM32_PLL1_DIVP_VALUE 1
#define STM32_PLL1_DIVQ_VALUE 10 #define STM32_PLL1_DIVQ_VALUE 5
#define STM32_PLL1_DIVR_VALUE 4 #define STM32_PLL1_DIVR_VALUE 5
#define STM32_PLL2_ENABLED TRUE #define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE #define STM32_PLL2_P_ENABLED TRUE
#define STM32_PLL2_Q_ENABLED TRUE #define STM32_PLL2_Q_ENABLED TRUE
@ -97,9 +97,9 @@
#define STM32_PLL2_DIVM_VALUE 8 #define STM32_PLL2_DIVM_VALUE 8
#define STM32_PLL2_DIVN_VALUE 400 #define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0 #define STM32_PLL2_FRACN_VALUE 0
#define STM32_PLL2_DIVP_VALUE 40 #define STM32_PLL2_DIVP_VALUE 50
#define STM32_PLL2_DIVQ_VALUE 8 #define STM32_PLL2_DIVQ_VALUE 4
#define STM32_PLL2_DIVR_VALUE 8 #define STM32_PLL2_DIVR_VALUE 4
#define STM32_PLL3_ENABLED TRUE #define STM32_PLL3_ENABLED TRUE
#define STM32_PLL3_P_ENABLED TRUE #define STM32_PLL3_P_ENABLED TRUE
#define STM32_PLL3_Q_ENABLED TRUE #define STM32_PLL3_Q_ENABLED TRUE
@ -107,9 +107,9 @@
#define STM32_PLL3_DIVM_VALUE 8 #define STM32_PLL3_DIVM_VALUE 8
#define STM32_PLL3_DIVN_VALUE 240 #define STM32_PLL3_DIVN_VALUE 240
#define STM32_PLL3_FRACN_VALUE 0 #define STM32_PLL3_FRACN_VALUE 0
#define STM32_PLL3_DIVP_VALUE 10 #define STM32_PLL3_DIVP_VALUE 5
#define STM32_PLL3_DIVQ_VALUE 10 #define STM32_PLL3_DIVQ_VALUE 5
#define STM32_PLL3_DIVR_VALUE 10 #define STM32_PLL3_DIVR_VALUE 5
/* /*
* Core clocks dynamic settings (can be changed at runtime). * Core clocks dynamic settings (can be changed at runtime).

34
os/hal/boards/ST_NUCLEO144_H7A3ZI_Q/board.h
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@ -59,7 +59,7 @@
/* /*
* IO pins assignments. * IO pins assignments.
*/ */
#define GPIOA_BUTTON 0U #define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U #define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U #define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U #define GPIOA_PIN3 3U
@ -110,7 +110,7 @@
#define GPIOC_PIN10 10U #define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U #define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U #define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U #define GPIOC_BUTTON 13U
#define GPIOC_OSC32_IN 14U #define GPIOC_OSC32_IN 14U
#define GPIOC_OSC32_OUT 15U #define GPIOC_OSC32_OUT 15U
@ -256,7 +256,6 @@
/* /*
* IO lines assignments. * IO lines assignments.
*/ */
#define LINE_BUTTON PAL_LINE(GPIOA, 0U)
#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) #define LINE_USB_SOF PAL_LINE(GPIOA, 8U)
#define LINE_MCO1 PAL_LINE(GPIOA, 8U) #define LINE_MCO1 PAL_LINE(GPIOA, 8U)
#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) #define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)
@ -272,6 +271,7 @@
#define LINE_SWO PAL_LINE(GPIOB, 3U) #define LINE_SWO PAL_LINE(GPIOB, 3U)
#define LINE_LED3 PAL_LINE(GPIOB, 14U) #define LINE_LED3 PAL_LINE(GPIOB, 14U)
#define LINE_LED_RED PAL_LINE(GPIOB, 14U) #define LINE_LED_RED PAL_LINE(GPIOB, 14U)
#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) #define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) #define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) #define LINE_USART3_RX PAL_LINE(GPIOD, 8U)
@ -326,7 +326,7 @@
/* /*
* GPIOA setup: * GPIOA setup:
* *
* PA0 - BUTTON (input pullup). * PA0 - PIN0 (input pullup).
* PA1 - PIN1 (input pullup). * PA1 - PIN1 (input pullup).
* PA2 - PIN2 (input pullup). * PA2 - PIN2 (input pullup).
* PA3 - PIN3 (input pullup). * PA3 - PIN3 (input pullup).
@ -343,7 +343,7 @@
* PA14 - SWCLK (alternate 0). * PA14 - SWCLK (alternate 0).
* PA15 - T_JTDI (alternate 0). * PA15 - T_JTDI (alternate 0).
*/ */
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ #define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
PIN_MODE_INPUT(GPIOA_PIN1) | \ PIN_MODE_INPUT(GPIOA_PIN1) | \
PIN_MODE_INPUT(GPIOA_PIN2) | \ PIN_MODE_INPUT(GPIOA_PIN2) | \
PIN_MODE_INPUT(GPIOA_PIN3) | \ PIN_MODE_INPUT(GPIOA_PIN3) | \
@ -359,7 +359,7 @@
PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
PIN_MODE_ALTERNATE(GPIOA_T_JTDI)) PIN_MODE_ALTERNATE(GPIOA_T_JTDI))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ #define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
@ -375,7 +375,7 @@
PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI)) PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_BUTTON) | \ #define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \ PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \ PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \ PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
@ -391,7 +391,7 @@
PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
PIN_OSPEED_HIGH(GPIOA_T_JTDI)) PIN_OSPEED_HIGH(GPIOA_T_JTDI))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_BUTTON) | \ #define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
@ -407,7 +407,7 @@
PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
PIN_PUPDR_PULLUP(GPIOA_T_JTDI)) PIN_PUPDR_PULLUP(GPIOA_T_JTDI))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ #define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
PIN_ODR_HIGH(GPIOA_PIN1) | \ PIN_ODR_HIGH(GPIOA_PIN1) | \
PIN_ODR_HIGH(GPIOA_PIN2) | \ PIN_ODR_HIGH(GPIOA_PIN2) | \
PIN_ODR_HIGH(GPIOA_PIN3) | \ PIN_ODR_HIGH(GPIOA_PIN3) | \
@ -423,7 +423,7 @@
PIN_ODR_HIGH(GPIOA_SWDIO) | \ PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \ PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_T_JTDI)) PIN_ODR_HIGH(GPIOA_T_JTDI))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ #define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
PIN_AFIO_AF(GPIOA_PIN2, 0U) | \ PIN_AFIO_AF(GPIOA_PIN2, 0U) | \
PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
@ -573,7 +573,7 @@
* PC10 - PIN10 (input pullup). * PC10 - PIN10 (input pullup).
* PC11 - PIN11 (input pullup). * PC11 - PIN11 (input pullup).
* PC12 - PIN12 (input pullup). * PC12 - PIN12 (input pullup).
* PC13 - PIN13 (input pullup). * PC13 - BUTTON (input floating).
* PC14 - OSC32_IN (input floating). * PC14 - OSC32_IN (input floating).
* PC15 - OSC32_OUT (input floating). * PC15 - OSC32_OUT (input floating).
*/ */
@ -590,7 +590,7 @@
PIN_MODE_INPUT(GPIOC_PIN10) | \ PIN_MODE_INPUT(GPIOC_PIN10) | \
PIN_MODE_INPUT(GPIOC_PIN11) | \ PIN_MODE_INPUT(GPIOC_PIN11) | \
PIN_MODE_INPUT(GPIOC_PIN12) | \ PIN_MODE_INPUT(GPIOC_PIN12) | \
PIN_MODE_INPUT(GPIOC_PIN13) | \ PIN_MODE_INPUT(GPIOC_BUTTON) | \
PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
PIN_MODE_INPUT(GPIOC_OSC32_OUT)) PIN_MODE_INPUT(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ #define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
@ -606,7 +606,7 @@
PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \ #define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \
@ -622,7 +622,7 @@
PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
PIN_OSPEED_VERYLOW(GPIOC_PIN13) | \ PIN_OSPEED_VERYLOW(GPIOC_BUTTON) | \
PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \
PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ #define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
@ -638,7 +638,7 @@
PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ #define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
@ -654,7 +654,7 @@
PIN_ODR_HIGH(GPIOC_PIN10) | \ PIN_ODR_HIGH(GPIOC_PIN10) | \
PIN_ODR_HIGH(GPIOC_PIN11) | \ PIN_ODR_HIGH(GPIOC_PIN11) | \
PIN_ODR_HIGH(GPIOC_PIN12) | \ PIN_ODR_HIGH(GPIOC_PIN12) | \
PIN_ODR_HIGH(GPIOC_PIN13) | \ PIN_ODR_HIGH(GPIOC_BUTTON) | \
PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
PIN_ODR_HIGH(GPIOC_OSC32_OUT)) PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ #define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
@ -670,7 +670,7 @@
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))

6
os/hal/boards/ST_NUCLEO144_H7A3ZI_Q/cfg/board.chcfg
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@ -23,7 +23,7 @@
<ports> <ports>
<GPIOA> <GPIOA>
<pin0 <pin0
ID="BUTTON" ID=""
Type="PushPull" Type="PushPull"
Level="High" Level="High"
Speed="Minimum" Speed="Minimum"
@ -387,11 +387,11 @@
Mode="Input" Mode="Input"
Alternate="0" /> Alternate="0" />
<pin13 <pin13
ID="" ID="BUTTON"
Type="PushPull" Type="PushPull"
Level="High" Level="High"
Speed="Minimum" Speed="Minimum"
Resistor="PullUp" Resistor="Floating"
Mode="Input" Mode="Input"
Alternate="0" /> Alternate="0" />
<pin14 <pin14

8
os/hal/ports/STM32/STM32H7xx/hal_lld_type3.h
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@ -977,6 +977,14 @@
#define STM32_CDCPRE STM32_CDCPRE_DIV1 #define STM32_CDCPRE STM32_CDCPRE_DIV1
#endif #endif
/**
* @brief Clock domain 2 peripherals bus prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_CDPPRE) || defined(__DOXYGEN__)
#define STM32_CDPPRE STM32_CDPPRE_DIV1
#endif
/** /**
* @brief Clock domain HPRE prescaler. * @brief Clock domain HPRE prescaler.
* @note This setting can be modified at runtime. * @note This setting can be modified at runtime.

2
readme.txt
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@ -85,7 +85,7 @@
- NEW: Modified SDMMCv2 to allow for uncached buffers, tested on STM32H7xx. - NEW: Modified SDMMCv2 to allow for uncached buffers, tested on STM32H7xx.
- NEW: Added OCTOSPIv2 driver using MDMA for STM32H7xx. - NEW: Added OCTOSPIv2 driver using MDMA for STM32H7xx.
- NEW: Added demos for STM32H723ZG Nucleo144 and STM32H735ZI Discovery boards. - NEW: Added demos for STM32H723ZG Nucleo144 and STM32H735ZI Discovery boards.
- NEW: Added support for STM32H723/25/33/35. - NEW: Added support for STM32H723/25/33/35/A3/B3/A3Q/B3Q.
- NEW: Updated ST Cube headers for STM32H7xx. - NEW: Updated ST Cube headers for STM32H7xx.
- NEW: Added a Posix-favored shell named "msh" (Mini Shell). The shell is able - NEW: Added a Posix-favored shell named "msh" (Mini Shell). The shell is able
to run sub-apps inside the same sandbox. The shell can either be placed to run sub-apps inside the same sandbox. The shell can either be placed