mirror of https://github.com/rusefi/ChibiOS.git
Reviewed RCC macros.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11198 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
71c54e625e
commit
f7051186ae
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@ -749,66 +749,82 @@
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* @{
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*/
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/**
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* @brief Enables the OTG_FS peripheral clock.
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* @brief Enables the USB1_OTG_HS peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
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#define rccEnableUSB1_OTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSEN, lp)
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/**
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* @brief Disables the OTG_FS peripheral clock.
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* @brief Disables the USB1_OTG_HS peripheral clock.
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*
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* @api
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*/
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#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
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#define rccDisableUSB1_OTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSEN)
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/**
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* @brief Resets the OTG_FS peripheral.
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* @brief Resets the USB1_OTG_HS peripheral.
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*
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* @api
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*/
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#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
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#define rccResetUSB1_OTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB1OTGHSRST)
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/**
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* @brief Enables the OTG_HS peripheral clock.
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* @brief Enables the USB2_OTG_HS peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
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#define rccEnableUSB2_OTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSEN, lp)
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/**
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* @brief Disables the OTG_HS peripheral clock.
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* @brief Disables the USB2_OTG_HS peripheral clock.
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*
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* @api
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*/
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#define rccDisableOTG_HS() rccDisableAHB1(RCC_AHB1ENR_OTGHSEN)
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#define rccDisableUSB2_OTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSEN)
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/**
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* @brief Resets the OTG_HS peripheral.
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* @brief Resets the USB2_OTG_HS peripheral.
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*
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* @api
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*/
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#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)
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#define rccResetUSB2_OTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGHSRST)
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/**
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* @brief Enables the OTG_HS peripheral clock.
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* @brief Enables the USB1_OTG_HS ULPI peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
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#define rccEnableUSB1_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN, lp)
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/**
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* @brief Disables the OTG_HS peripheral clock.
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* @brief Disables the USB1_OTG_HS peripheral clock.
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*
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* @api
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*/
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#define rccDisableOTG_HSULPI() rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN)
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#define rccDisableUSB1_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN)
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/**
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* @brief Enables the USB2_OTG_HS ULPI peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableUSB2_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSULPIEN, lp)
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/**
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* @brief Disables the USB2_OTG_HS peripheral clock.
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*
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* @api
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*/
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#define rccDisableUSB2_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSULPIEN)
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/** @} */
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/**
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@ -850,21 +866,21 @@
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*
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* @api
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*/
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#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
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#define rccEnableSDMMC1(lp) rccEnableAHB3(RCC_AHB3ENR_SDMMC1EN, lp)
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/**
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* @brief Disables the SDMMC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
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#define rccDisableSDMMC1() rccDisableAHB3(RCC_AHB3ENR_SDMMC1EN)
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/**
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* @brief Resets the SDMMC1 peripheral.
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*
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* @api
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*/
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#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
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#define rccResetSDMMC1() rccResetAHB3(RCC_AHB3RSTR_SDMMC1RST)
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/** @} */
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/**
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@ -993,21 +1009,21 @@
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*
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* @api
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*/
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#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp)
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#define rccEnableSPI6(lp) rccEnableAPB4(RCC_APB4ENR_SPI6EN, lp)
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/**
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* @brief Disables the SPI6 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSPI6() rccDisableAPB2(RCC_APB2ENR_SPI6EN)
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#define rccDisableSPI6() rccDisableAPB4(RCC_APB4ENR_SPI6EN)
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/**
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* @brief Resets the SPI6 peripheral.
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*
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* @api
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*/
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#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST)
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#define rccResetSPI6() rccResetAPB4(RCC_APB4RSTR_SPI6RST)
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/** @} */
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/**
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@ -1268,6 +1284,75 @@
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* @api
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*/
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#define rccResetTIM14() rccResetAPB1L(RCC_APB1LRSTR_TIM14RST)
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/**
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* @brief Enables the TIM15 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
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/**
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* @brief Disables the TIM15 peripheral clock.
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*
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* @api
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*/
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#define rccDisableTIM15(...) rccDisableAPB2(RCC_APB2ENR_TIM15EN)
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/**
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* @brief Resets the TIM15 peripheral.
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*
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* @api
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*/
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#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
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/**
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* @brief Enables the TIM16 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
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/**
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* @brief Disables the TIM16 peripheral clock.
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*
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* @api
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*/
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#define rccDisableTIM16(...) rccDisableAPB2(RCC_APB2ENR_TIM16EN)
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/**
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* @brief Resets the TIM16 peripheral.
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*
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* @api
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*/
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#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
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/**
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* @brief Enables the TIM17 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
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/**
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* @brief Disables the TIM17 peripheral clock.
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*
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* @api
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*/
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#define rccDisableTIM17(...) rccDisableAPB2(RCC_APB2ENR_TIM17EN)
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/**
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* @brief Resets the TIM17 peripheral.
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*
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* @api
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*/
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#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
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/** @} */
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/**
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@ -1470,21 +1555,21 @@
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*
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* @api
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*/
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#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp)
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#define rccEnableLTDC(lp) rccEnableAPB3(RCC_APB3ENR_LTDCEN, lp)
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/**
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* @brief Disables the LTDC peripheral clock.
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. *
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* @api
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*/
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#define rccDisableLTDC() rccDisableAPB2(RCC_APB2ENR_LTDCEN)
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#define rccDisableLTDC() rccDisableAPB3(RCC_APB3ENR_LTDCEN)
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/**
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* @brief Resets the LTDC peripheral.
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*
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* @api
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*/
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#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
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#define rccResetLTDC() rccResetAPB3(RCC_APB3RSTR_LTDCRST)
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/**
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* @name DMA2D peripheral specific RCC operations
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@ -1497,21 +1582,21 @@
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*
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* @api
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*/
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#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
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#define rccEnableDMA2D(lp) rccEnableAHB3(RCC_AHB3ENR_DMA2DEN, lp)
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/**
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* @brief Disables the DMA2D peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA2D() rccDisableAHB1(RCC_AHB1ENR_DMA2DEN)
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#define rccDisableDMA2D() rccDisableAHB3(RCC_AHB3ENR_DMA2DEN)
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/**
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* @brief Resets the DMA2D peripheral.
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*
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* @api
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*/
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#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
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#define rccResetDMA2D() rccResetAHB3(RCC_AHB3RSTR_DMA2DRST)
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/** @} */
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/**
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