mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9472 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
f5be820e9c
commit
fdcdb6e916
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@ -44,6 +44,9 @@ endif
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ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
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HALSRC += $(CHIBIOS)/os/hal/src/hal_pwm.c
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endif
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ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
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HALSRC += $(CHIBIOS)/os/hal/src/hal_qspi.c
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endif
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ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
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HALSRC += $(CHIBIOS)/os/hal/src/hal_rtc.c
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endif
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@ -85,6 +88,7 @@ HALSRC = $(CHIBIOS)/os/hal/src/hal.c \
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$(CHIBIOS)/os/hal/src/hal_mmc_spi.c \
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$(CHIBIOS)/os/hal/src/hal_pal.c \
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$(CHIBIOS)/os/hal/src/hal_pwm.c \
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$(CHIBIOS)/os/hal/src/hal_qspi.c \
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$(CHIBIOS)/os/hal/src/hal_rtc.c \
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$(CHIBIOS)/os/hal/src/hal_sdc.c \
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$(CHIBIOS)/os/hal/src/hal_serial.c \
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@ -29,6 +29,83 @@
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#include "board.h"
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#include "halconf.h"
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/* Error checks on the configuration header file.*/
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#if !defined(HAL_USE_PAL)
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#define HAL_USE_PAL FALSE
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#endif
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#if !defined(HAL_USE_ADC)
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#define HAL_USE_ADC FALSE
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#endif
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#if !defined(HAL_USE_CAN)
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#define HAL_USE_CAN FALSE
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#endif
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#if !defined(HAL_USE_DAC)
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#define HAL_USE_DAC FALSE
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#endif
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#if !defined(HAL_USE_EXT)
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#define HAL_USE_ETX FALSE
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#endif
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#if !defined(HAL_USE_GPT)
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#define HAL_USE_GPT FALSE
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#endif
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#if !defined(HAL_USE_I2C)
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#define HAL_USE_I2C FALSE
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#endif
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#if !defined(HAL_USE_I2S)
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#define HAL_USE_I2S FALSE
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#endif
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#if !defined(HAL_USE_ICU)
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#define HAL_USE_ICU FALSE
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#endif
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#if !defined(HAL_USE_MAC)
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#define HAL_USE_MAC FALSE
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#endif
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#if !defined(HAL_USE_PWM)
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#define HAL_USE_PWM FALSE
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#endif
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#if !defined(HAL_USE_QSPI)
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#define HAL_USE_QSPI FALSE
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#endif
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#if !defined(HAL_USE_RTC)
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#define HAL_USE_RTC FALSE
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#endif
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#if !defined(HAL_USE_SERIAL)
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#define HAL_USE_SERIAL FALSE
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#endif
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#if !defined(HAL_USE_SDC)
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#define HAL_USE_SDC FALSE
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#endif
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#if !defined(HAL_USE_SPI)
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#define HAL_USE_SPI FALSE
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#endif
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#if !defined(HAL_USE_UART)
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#define HAL_USE_UART FALSE
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#endif
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#if !defined(HAL_USE_USB)
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#define HAL_USE_USB FALSE
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#endif
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#if !defined(HAL_USE_WDG)
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#define HAL_USE_WDG FALSE
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#endif
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#include "hal_lld.h"
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/* Abstract interfaces.*/
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@ -54,6 +131,7 @@
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#include "hal_icu.h"
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#include "hal_mac.h"
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#include "hal_pwm.h"
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#include "hal_qspi.h"
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#include "hal_rtc.h"
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#include "hal_serial.h"
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#include "hal_sdc.h"
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@ -31,6 +31,10 @@
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Transfer options
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* @{
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*/
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#define QSPI_CFG_CMD_MASK (0xFFU << 0U)
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#define QSPI_CFG_CMD(n) ((n) << 0U)
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#define QSPI_CFG_CMD_MODE_MASK (3U << 8U)
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#define QSPI_CFG_ADDR_SIZE_16 (1U << 12U)
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#define QSPI_CFG_ADDR_SIZE_24 (2U << 12U)
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#define QSPI_CFG_ADDR_SIZE_32 (3U << 12U)
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#define QSPI_CFG_AB_MODE_MASK (3U << 14U)
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#define QSPI_CFG_AB_MODE_NONE (0U << 14U)
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#define QSPI_CFG_AB_MODE_ONE_LINE (1U << 14U)
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#define QSPI_CFG_AB_MODE_TWO_LINES (2U << 14U)
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#define QSPI_CFG_AB_MODE_FOUR_LINES (3U << 14U)
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#define QSPI_CFG_AB_SIZE_MASK (3U << 16U)
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#define QSPI_CFG_AB_SIZE_8 (0U << 16U)
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#define QSPI_CFG_AB_SIZE_16 (1U << 16U)
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#define QSPI_CFG_AB_SIZE_24 (2U << 16U)
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#define QSPI_CFG_AB_SIZE_32 (3U << 16U)
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#define QSPI_CFG_ALT_MODE_MASK (3U << 14U)
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#define QSPI_CFG_ALT_MODE_NONE (0U << 14U)
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#define QSPI_CFG_ALT_MODE_ONE_LINE (1U << 14U)
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#define QSPI_CFG_ALT_MODE_TWO_LINES (2U << 14U)
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#define QSPI_CFG_ALT_MODE_FOUR_LINES (3U << 14U)
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#define QSPI_CFG_ALT_SIZE_MASK (3U << 16U)
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#define QSPI_CFG_ALT_SIZE_8 (0U << 16U)
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#define QSPI_CFG_ALT_SIZE_16 (1U << 16U)
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#define QSPI_CFG_ALT_SIZE_24 (2U << 16U)
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#define QSPI_CFG_ALT_SIZE_32 (3U << 16U)
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#define QSPI_CFG_DUMMY_CYCLES_MASK (0x1FU << 18U)
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#define QSPI_CFG_DUMMY_CYCLES(n) ((n) << 18U)
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#define QSPI_CFG_DATA_MODE_MASK (3U << 24U)
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#define QSPI_CFG_F_MODE_FOUR_LINES (3U << 26U)
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#define QSPI_CFG_SIOO (1U << 28U)
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#define QSPI_CFG_DDRM (1U << 31U)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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@ -118,15 +123,15 @@ typedef enum {
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} qspistate_t;
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/**
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* @brief Type of a QSPI transaction descriptor.
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* @brief Type of a QSPI command descriptor.
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*/
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typedef struct {
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uint32_t cfg;
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uint32_t address;
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uint32_t alternate;
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} qspitransaction_t;
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uint32_t addr;
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uint32_t alt;
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} qspi_command_t;
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#include "hal_spi_lld.h"
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#include "hal_qspi_lld.h"
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/*===========================================================================*/
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/* Driver macros. */
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@ -142,14 +147,15 @@ typedef struct {
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] n number of bytes to send
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of bytes to send or zero if no data phase
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @iclass
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*/
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#define qspiStartSendI(qspip, n, txbuf) { \
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#define qspiStartSendI(qspip, cmd, n, txbuf) { \
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(qspip)->state = QSPI_ACTIVE; \
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qspi_lld_send(qspip, n, txbuf); \
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qspi_lld_send(qspip, cmd, n, txbuf); \
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}
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/**
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@ -158,14 +164,15 @@ typedef struct {
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] n number of bytes to receive
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of bytes to receive or zero if no data phase
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* @param[out] rxbuf the pointer to the receive buffer
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*
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* @iclass
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*/
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#define qspiStartReceiveI(qspip, n, rxbuf) { \
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#define qspiStartReceiveI(qspip, cmd, n, rxbuf) { \
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(qspip)->state = QSPI_ACTIVE; \
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qspi_lld_receive(qspip, n, rxbuf); \
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qspi_lld_receive(qspip, cmd, n, rxbuf); \
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}
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/** @} */
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@ -228,11 +235,15 @@ extern "C" {
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void qspiObjectInit(QSPIDriver *qspip);
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void qspiStart(QSPIDriver *qspip, const QSPIConfig *config);
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void qspiStop(QSPIDriver *qspip);
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void qspiStartSend(QSPIDriver *qspip, size_t n, const void *txbuf);
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void qspiStartReceive(QSPIDriver *qspip, size_t n, void *rxbuf);
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void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf);
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void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, uint8_t *rxbuf);
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#if QSPI_USE_WAIT == TRUE
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void qspiSend(QSPIDriver *qspip, size_t n, const void *txbuf);
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void qspiReceive(QSPIDriver *qspip, size_t n, void *rxbuf);
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void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf);
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void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, uint8_t *rxbuf);
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#endif
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#if QSPI_USE_MUTUAL_EXCLUSION == TRUE
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void qspiAcquireBus(QSPIDriver *qspip);
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@ -0,0 +1,212 @@
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/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file QUADSPIv1/hal_qspi_lld.c
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* @brief STM32 QSPI subsystem low level driver source.
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*
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* @addtogroup QSPI
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_QSPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define SPI1_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_QSPI_QUADSPI1_DMA_STREAM, \
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STM32_QUADSPI1_RX_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief SPI1 driver identifier.*/
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#if STM32_QSPI_USE_QUADSPI1 || defined(__DOXYGEN__)
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SPIDriver QSPID1;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared service routine.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void qspi_lld_serve_dma_interrupt(QSPIDriver *qspip, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_QSPI_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_QSPI_DMA_ERROR_HOOK(qspip);
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}
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#else
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(void)flags;
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#endif
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}
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/**
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* @brief Shared service routine.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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*/
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static void qspi_lld_serve_interrupt(QSPIDriver *qspip) {
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/* Stop everything.*/
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dmaStreamDisable(qspip->dma);
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/* Portable QSPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_qspi_isr_code(qspip);
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level SPI driver initialization.
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*
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* @notapi
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*/
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void qspi_lld_init(void) {
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#if STM32_QSPI_USE_QUADSPI1
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qspiObjectInit(&QSPID1);
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QSPID1.spi = SPI1;
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QSPID1.dma = STM32_DMA_STREAM(STM32_QSPI_QUADSPI1_DMA_STREAM);
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QSPID1.dmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_QSPI_QUADSPI1_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_BYTE |
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STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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#endif
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}
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/**
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* @brief Configures and activates the QSPI peripheral.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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*
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* @notapi
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*/
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void qspi_lld_start(QSPIDriver *qspip) {
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uint32_t ds;
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/* If in stopped state then enables the SPI and DMA clocks.*/
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if (qspip->state == QSPI_STOP) {
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#if STM32_SPI_USE_SPI1
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if (&SPID1 == qspip) {
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rccEnableQUADSPI1(FALSE);
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}
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#endif
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/* QSPI setup and enable.*/
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// spip->spi->CR1 = 0;
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// spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR;
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// spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |
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// SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
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// spip->spi->CR1 |= SPI_CR1_SPE;
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}
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/**
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* @brief Deactivates the QSPI peripheral.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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*
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* @notapi
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*/
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void qspi_lld_stop(QSPIDriver *qspip) {
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/* If in ready state then disables the SPI clock.*/
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if (qspip->state == QSPI_READY) {
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/* QSPI disable.*/
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// spip->spi->CR1 = 0;
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// spip->spi->CR2 = 0;
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dmaStreamRelease(qspip->dma);
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#if STM32_QSPI_USE_QUADSPI1
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if (&QSPID1 == qspip)
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rccDisableQUADSPI1(FALSE);
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#endif
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}
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}
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/**
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* @brief Sends data over the QSPI bus.
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* @details This asynchronous function starts a transmit operation.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] qspip pointer to the @p QSPIDriver object
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of words to send
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, const uint8_t *txbuf) {
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dmaStreamSetMemory0(qspip->dma, txbuf);
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dmaStreamSetTransactionSize(qspip->dma, n);
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dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_M2P);
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dmaStreamEnable(qspip->dma);
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}
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/**
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* @brief Receives data from the QSPI bus.
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* @details This asynchronous function starts a receive operation.
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* @post At the end of the operation the configured callback is invoked.
|
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*
|
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* @param[in] qspip pointer to the @p QSPIDriver object
|
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* @param[in] cmd pointer to the command descriptor
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* @param[in] n number of words to receive
|
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* @param[out] rxbuf the pointer to the receive buffer
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*
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* @notapi
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*/
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void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
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size_t n, uint8_t *rxbuf) {
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dmaStreamSetMemory0(qspip->dma, rxbuf);
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dmaStreamSetTransactionSize(qspip->dma, n);
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dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_P2M);
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dmaStreamEnable(qspip->dmarx);
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}
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|
||||
#endif /* HAL_USE_QSPI */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,541 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file QUADSPIv1/hal_qspi_lld.h
|
||||
* @brief STM32 QSPI subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HAL_SPI_LLD_H
|
||||
#define HAL_SPI_LLD_H
|
||||
|
||||
#if HAL_USE_QSPI || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief SPI1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for SPI1 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI2 driver enable switch.
|
||||
* @details If set to @p TRUE the support for SPI2 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI3 driver enable switch.
|
||||
* @details If set to @p TRUE the support for SPI3 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI4 driver enable switch.
|
||||
* @details If set to @p TRUE the support for SPI4 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_USE_SPI4 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI5 driver enable switch.
|
||||
* @details If set to @p TRUE the support for SPI5 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_USE_SPI5 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI6 driver enable switch.
|
||||
* @details If set to @p TRUE the support for SPI6 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_USE_SPI6 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI5 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI6 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI1 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA streams but
|
||||
* because of the streams ordering the RX stream has always priority
|
||||
* over the TX stream.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI2 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA streams but
|
||||
* because of the streams ordering the RX stream has always priority
|
||||
* over the TX stream.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI3 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA streams but
|
||||
* because of the streams ordering the RX stream has always priority
|
||||
* over the TX stream.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI4 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA streams but
|
||||
* because of the streams ordering the RX stream has always priority
|
||||
* over the TX stream.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI5 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA streams but
|
||||
* because of the streams ordering the RX stream has always priority
|
||||
* over the TX stream.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI6 DMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX DMA streams but
|
||||
* because of the streams ordering the RX stream has always priority
|
||||
* over the TX stream.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI DMA error hook.
|
||||
*/
|
||||
#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
|
||||
#error "SPI1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
|
||||
#error "SPI2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
|
||||
#error "SPI3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
|
||||
#error "SPI4 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
|
||||
#error "SPI5 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
|
||||
#error "SPI6 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
|
||||
!STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
|
||||
#error "SPI driver activated but no SPI peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI2"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI3"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI4"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI5"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI6"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI2"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI3"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI4"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI5"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI6"
|
||||
#endif
|
||||
|
||||
/* The following checks are only required when there is a DMA able to
|
||||
reassign streams to different channels.*/
|
||||
#if STM32_ADVANCED_DMA
|
||||
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
|
||||
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
|
||||
!defined(STM32_SPI_SPI1_TX_DMA_STREAM))
|
||||
#error "SPI1 DMA streams not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
|
||||
!defined(STM32_SPI_SPI2_TX_DMA_STREAM))
|
||||
#error "SPI2 DMA streams not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
|
||||
!defined(STM32_SPI_SPI3_TX_DMA_STREAM))
|
||||
#error "SPI3 DMA streams not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
|
||||
!defined(STM32_SPI_SPI4_TX_DMA_STREAM))
|
||||
#error "SPI4 DMA streams not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
|
||||
!defined(STM32_SPI_SPI5_TX_DMA_STREAM))
|
||||
#error "SPI5 DMA streams not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \
|
||||
!defined(STM32_SPI_SPI6_TX_DMA_STREAM))
|
||||
#error "SPI6 DMA streams not defined"
|
||||
#endif
|
||||
|
||||
/* Check on the validity of the assigned DMA channels.*/
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI1 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI1 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI2 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI2 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI3 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI3 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI4 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI4 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI5 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI5 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI6 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
|
||||
#error "invalid DMA stream associated to SPI6 TX"
|
||||
#endif
|
||||
#endif /* STM32_ADVANCED_DMA */
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an SPI driver.
|
||||
*/
|
||||
typedef struct SPIDriver SPIDriver;
|
||||
|
||||
/**
|
||||
* @brief SPI notification callback type.
|
||||
*
|
||||
* @param[in] spip pointer to the @p SPIDriver object triggering the
|
||||
* callback
|
||||
*/
|
||||
typedef void (*spicallback_t)(SPIDriver *spip);
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Operation complete callback or @p NULL.
|
||||
*/
|
||||
spicallback_t end_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief The chip select line port.
|
||||
*/
|
||||
ioportid_t ssport;
|
||||
/**
|
||||
* @brief The chip select line pad number.
|
||||
*/
|
||||
uint16_t sspad;
|
||||
/**
|
||||
* @brief SPI CR1 register initialization data.
|
||||
*/
|
||||
uint16_t cr1;
|
||||
/**
|
||||
* @brief SPI CR2 register initialization data.
|
||||
*/
|
||||
uint16_t cr2;
|
||||
} SPIConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an SPI driver.
|
||||
*/
|
||||
struct SPIDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
spistate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const SPIConfig *config;
|
||||
#if SPI_USE_WAIT || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
thread_reference_t thread;
|
||||
#endif /* SPI_USE_WAIT */
|
||||
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
mutex_t mutex;
|
||||
#endif /* SPI_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(SPI_DRIVER_EXT_FIELDS)
|
||||
SPI_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the SPIx registers block.
|
||||
*/
|
||||
SPI_TypeDef *spi;
|
||||
/**
|
||||
* @brief Receive DMA stream.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmarx;
|
||||
/**
|
||||
* @brief Transmit DMA stream.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmatx;
|
||||
/**
|
||||
* @brief RX DMA mode bit mask.
|
||||
*/
|
||||
uint32_t rxdmamode;
|
||||
/**
|
||||
* @brief TX DMA mode bit mask.
|
||||
*/
|
||||
uint32_t txdmamode;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID1;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID2;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID3;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID4;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID5;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID6;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void qspi_lld_init(void);
|
||||
void qspi_lld_start(SPIDriver *spip);
|
||||
void qspi_lld_stop(SPIDriver *spip);
|
||||
void qspi_lld_send(SPIDriver *spip, size_t n, const uint8_t *txbuf);
|
||||
void qspi_lld_receive(SPIDriver *spip, size_t n, uint8_t *rxbuf);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_QSPI */
|
||||
|
||||
#endif /* HAL_SPI_LLD_H */
|
||||
|
||||
/** @} */
|
|
@ -128,18 +128,21 @@ void qspiStop(QSPIDriver *qspip) {
|
|||
* @post At the end of the operation the configured callback is invoked.
|
||||
*
|
||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||
* @param[in] n number of words to send
|
||||
* @param[in] cmd pointer to the command descriptor
|
||||
* @param[in] n number of words to send or zero if no data phase
|
||||
* @param[in] txbuf the pointer to the transmit buffer
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void qspiStartSend(QSPIDriver *qspip, size_t n, const void *txbuf) {
|
||||
void qspiStartSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||
size_t n, const uint8_t *txbuf) {
|
||||
|
||||
osalDbgCheck((qspip != NULL) && (n > 0U) && (txbuf != NULL));
|
||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||
osalDbgCheck((n == 0U) || ((n > 0U) && (txbuf != NULL)));
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||
qspiStartSendI(qspip, n, txbuf);
|
||||
qspiStartSendI(qspip, cmd, n, txbuf);
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
||||
|
@ -149,18 +152,21 @@ void qspiStartSend(QSPIDriver *qspip, size_t n, const void *txbuf) {
|
|||
* @post At the end of the operation the configured callback is invoked.
|
||||
*
|
||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||
* @param[in] n number of words to receive
|
||||
* @param[in] cmd pointer to the command descriptor
|
||||
* @param[in] n number of words to receive or zero if no data phase
|
||||
* @param[out] rxbuf the pointer to the receive buffer
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void qspiStartReceive(QSPIDriver *qspip, size_t n, void *rxbuf) {
|
||||
void qspiStartReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||
size_t n, uint8_t *rxbuf) {
|
||||
|
||||
osalDbgCheck((qspip != NULL) && (n > 0U) && (rxbuf != NULL));
|
||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||
osalDbgCheck((n == 0U) || ((n > 0U) && (rxbuf != NULL)));
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||
qspiStartReceiveI(qspip, n, rxbuf);
|
||||
qspiStartReceiveI(qspip, cmd, n, rxbuf);
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
||||
|
@ -172,23 +178,24 @@ void qspiStartReceive(QSPIDriver *qspip, size_t n, void *rxbuf) {
|
|||
* enabled.
|
||||
* @pre In order to use this function the driver must have been configured
|
||||
* without callbacks (@p end_cb = @p NULL).
|
||||
* @note The buffers are organized as uint8_t arrays for data sizes below
|
||||
* or equal to 8 bits else it is organized as uint16_t arrays.
|
||||
*
|
||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||
* @param[in] n number of words to send
|
||||
* @param[in] cmd pointer to the command descriptor
|
||||
* @param[in] n number of words to send or zero if no data phase
|
||||
* @param[in] txbuf the pointer to the transmit buffer
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void qspiSend(QSPIDriver *qspip, size_t n, const void *txbuf) {
|
||||
void qspiSend(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||
size_t n, const uint8_t *txbuf) {
|
||||
|
||||
osalDbgCheck((qspip != NULL) && (n > 0U) && (txbuf != NULL));
|
||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||
osalDbgCheck((n == 0U) || ((n > 0U) && (txbuf != NULL)));
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||
osalDbgAssert(qspip->config->end_cb == NULL, "has callback");
|
||||
qspiStartSendI(qspip, n, txbuf);
|
||||
qspiStartSendI(qspip, cmd, n, txbuf);
|
||||
(void) osalThreadSuspendS(&qspip->thread);
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
@ -200,23 +207,24 @@ void qspiSend(QSPIDriver *qspip, size_t n, const void *txbuf) {
|
|||
* enabled.
|
||||
* @pre In order to use this function the driver must have been configured
|
||||
* without callbacks (@p end_cb = @p NULL).
|
||||
* @note The buffers are organized as uint8_t arrays for data sizes below
|
||||
* or equal to 8 bits else it is organized as uint16_t arrays.
|
||||
*
|
||||
* @param[in] qspip pointer to the @p QSPIDriver object
|
||||
* @param[in] n number of words to receive
|
||||
* @param[in] cmd pointer to the command descriptor
|
||||
* @param[in] n number of words to receive or zero if no data phase
|
||||
* @param[out] rxbuf the pointer to the receive buffer
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void qspiReceive(QSPIDriver *qspip, size_t n, void *rxbuf) {
|
||||
void qspiReceive(QSPIDriver *qspip, const qspi_command_t *cmdp,
|
||||
size_t n, uint8_t *rxbuf) {
|
||||
|
||||
osalDbgCheck((qspip != NULL) && (n > 0U) && (rxbuf != NULL));
|
||||
osalDbgCheck((qspip != NULL) && (cmdp != NULL));
|
||||
osalDbgCheck((n == 0U) || ((n > 0U) && (rxbuf != NULL)));
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert(qspip->state == QSPI_READY, "not ready");
|
||||
osalDbgAssert(qspip->config->end_cb == NULL, "has callback");
|
||||
qspiStartReceiveI(qspip, n, rxbuf);
|
||||
qspiStartReceiveI(qspip, cmd, n, rxbuf);
|
||||
(void) osalThreadSuspendS(&qspip->thread);
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue