mirror of https://github.com/rusefi/ChibiOS.git
459 lines
18 KiB
C
459 lines
18 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2025 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32H5xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32H5xx_MCUCONF
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#define STM32H562_MCUCONF
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#define STM32H563_MCUCONF
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#define STM32H573_MCUCONF
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/*
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* HAL driver general settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_CLOCK_DYNAMIC FALSE
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/*
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* ICache settings.
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*/
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#define STM32_ICACHE_CR (ICACHE_CR_EN)
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#define STM32_ICACHE_CRR0 (0U)
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#define STM32_ICACHE_CRR1 (0U)
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#define STM32_ICACHE_CRR2 (0U)
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#define STM32_ICACHE_CRR3 (0U)
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/*
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* PWR settings.
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*/
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#define STM32_PWR_VOSCR STM32_VOS_RANGE0
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#define STM32_PWR_BDCR (0U)
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#define STM32_PWR_UCPDR (0U)
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#define STM32_PWR_SCCR (0U)
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#define STM32_PWR_VMCR (0U)
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#define STM32_PWR_USBSCR (0U)
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#define STM32_PWR_WUCR (0U)
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#define STM32_PWR_IORETR (0U)
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#define STM32_PWR_SECCFGR (0U)
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#define STM32_PWR_PRIVCFGR (0U)
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/*
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* Clock settings.
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*/
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#define STM32_HSI_ENABLED TRUE
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#define STM32_HSIDIV_VALUE 2
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#define STM32_HSI48_ENABLED FALSE
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#define STM32_CSI_ENABLED FALSE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_SW STM32_SW_PLL1P
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#define STM32_PLL1SRC STM32_PLL1SRC_HSE
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#define STM32_PLL1M_VALUE 4
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#define STM32_PLL1N_VALUE 250
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#define STM32_PLL1P_VALUE 2
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#define STM32_PLL1Q_VALUE 4
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#define STM32_PLL1R_VALUE 2
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#define STM32_PLL2SRC STM32_PLL2SRC_HSE
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#define STM32_PLL2M_VALUE 4
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#define STM32_PLL2N_VALUE 200
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#define STM32_PLL2P_VALUE 2
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#define STM32_PLL2Q_VALUE 2
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#define STM32_PLL2R_VALUE 2
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#define STM32_PLL3SRC STM32_PLL3SRC_HSE
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#define STM32_PLL3M_VALUE 4
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#define STM32_PLL3N_VALUE 240
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#define STM32_PLL3P_VALUE 2
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#define STM32_PLL3Q_VALUE 10
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#define STM32_PLL3R_VALUE 2
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV1
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_PPRE3 STM32_PPRE3_DIV1
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#define STM32_STOPWUCK STM32_STOPWUCK_HSI
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#define STM32_STOPKERWUCK STM32_STOPKERWUCK_HSI
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#define STM32_RTCPRE_VALUE STM32_RTCPRE_NOCLOCK
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE_VALUE STM32_MCO1PRE_NOCLOCK
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE_VALUE STM32_MCO2PRE_NOCLOCK
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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/*
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* Peripherals clock sources.
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*/
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#define STM32_USART1SEL STM32_USART1SEL_PCLK2
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#define STM32_USART2SEL STM32_USART2SEL_PCLK1
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#define STM32_USART3SEL STM32_USART3SEL_PCLK1
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#define STM32_UART4SEL STM32_UART4SEL_PCLK1
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#define STM32_UART5SEL STM32_UART5SEL_PCLK1
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#define STM32_USART6SEL STM32_USART6SEL_PCLK1
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#define STM32_UART7SEL STM32_UART7SEL_PCLK1
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#define STM32_UART8SEL STM32_UART8SEL_PCLK1
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#define STM32_UART9SEL STM32_UART9SEL_PCLK1
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#define STM32_USART10SEL STM32_USART10SEL_PCLK1
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#define STM32_USART11SEL STM32_USART11SEL_PCLK1
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#define STM32_UART12SEL STM32_UART12SEL_PCLK1
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK3
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#define STM32_TIMICSEL STM32_TIMICSEL_NOCLK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK3
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
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#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK3
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#define STM32_LPTIM4SEL STM32_LPTIM4SEL_PCLK3
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#define STM32_LPTIM5SEL STM32_LPTIM5SEL_PCLK3
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#define STM32_LPTIM6SEL STM32_LPTIM6SEL_PCLK3
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#define STM32_SPI1SEL STM32_SPI1SEL_PLL1Q
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#define STM32_SPI2SEL STM32_SPI2SEL_PLL1Q
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#define STM32_SPI3SEL STM32_SPI3SEL_PLL1Q
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#define STM32_SPI4SEL STM32_SPI4SEL_PCLK2
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#define STM32_SPI5SEL STM32_SPI5SEL_PCLK3
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#define STM32_SPI6SEL STM32_SPI6SEL_PCLK2
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#define STM32_OSPISEL STM32_OSPISEL_HCLK4
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#define STM32_SYSTICKSEL STM32_SYSTICKSEL_HCLKDIV8
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#define STM32_USBSEL STM32_USBSEL_NOCLOCK
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#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL1Q
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#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL1Q
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
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#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK3
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK3
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#define STM32_I3C1SEL STM32_I3C1SEL_PCLK1
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#define STM32_ADCDACSEL STM32_ADCDACSEL_HCLK
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#define STM32_DACSEL STM32_DACSEL_IGNORE
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#define STM32_RNGSEL STM32_RNGSEL_IGNORE
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#define STM32_CECSEL STM32_CECSEL_IGNORE
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#define STM32_FDCANSEL STM32_FDCANSEL_IGNORE
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#define STM32_SAI1SEL STM32_SAI1SEL_PLL1Q
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#define STM32_SAI2SEL STM32_SAI2SEL_PLL1Q
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#define STM32_CKPERSEL STM32_CKPERSEL_HSI
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_PRIORITY 6
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#define STM32_IRQ_EXTI6_PRIORITY 6
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#define STM32_IRQ_EXTI7_PRIORITY 6
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#define STM32_IRQ_EXTI8_PRIORITY 6
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#define STM32_IRQ_EXTI9_PRIORITY 6
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#define STM32_IRQ_EXTI10_PRIORITY 6
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#define STM32_IRQ_EXTI11_PRIORITY 6
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#define STM32_IRQ_EXTI12_PRIORITY 6
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#define STM32_IRQ_EXTI13_PRIORITY 6
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#define STM32_IRQ_EXTI14_PRIORITY 6
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#define STM32_IRQ_EXTI15_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_I2C1_PRIORITY 5
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#define STM32_IRQ_I2C2_PRIORITY 5
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#define STM32_IRQ_I2C3_PRIORITY 5
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#define STM32_IRQ_I2C4_PRIORITY 5
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#define STM32_IRQ_TIM1_BRK_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_TIM8_BRK_PRIORITY 7
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#define STM32_IRQ_TIM8_UP_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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#define STM32_IRQ_TIM12_PRIORITY 7
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#define STM32_IRQ_TIM13_PRIORITY 7
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#define STM32_IRQ_TIM14_PRIORITY 7
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#define STM32_IRQ_TIM15_PRIORITY 7
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#define STM32_IRQ_TIM16_PRIORITY 7
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#define STM32_IRQ_TIM17_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART3_PRIORITY 12
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#define STM32_IRQ_UART4_PRIORITY 12
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#define STM32_IRQ_UART5_PRIORITY 12
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#define STM32_IRQ_USART6_PRIORITY 12
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#define STM32_IRQ_UART7_PRIORITY 12
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#define STM32_IRQ_UART8_PRIORITY 12
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#define STM32_IRQ_UART9_PRIORITY 12
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#define STM32_IRQ_USART10_PRIORITY 12
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#define STM32_IRQ_USART11_PRIORITY 12
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#define STM32_IRQ_UART12_PRIORITY 12
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#define STM32_IRQ_LPUART1_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_DUAL_MODE FALSE
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_ADC1_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_ADC_ADC2_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC2_DMA_PRIORITY 2
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#define STM32_ADC_ADC1_IRQ_PRIORITY 5
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#define STM32_ADC_ADC2_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_FDCAN1 FALSE
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#define STM32_CAN_USE_FDCAN2 FALSE
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_DAC_DAC1_CH2_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM12 FALSE
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#define STM32_GPT_USE_TIM13 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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#define STM32_GPT_USE_TIM15 FALSE
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#define STM32_GPT_USE_TIM16 FALSE
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#define STM32_GPT_USE_TIM17 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_USE_I2C4 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_I2C4_DMA_PRIORITY 3
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#define STM32_I2C_I2C1_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_I2C_I2C2_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_I2C_I2C3_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_I2C_I2C4_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM12 FALSE
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#define STM32_ICU_USE_TIM15 FALSE
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#define STM32_ICU_USE_TIM16 FALSE
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#define STM32_ICU_USE_TIM17 FALSE
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/*
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* MAC driver system settings.
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*/
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#define STM32_MAC_TRANSMIT_BUFFERS 2
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#define STM32_MAC_RECEIVE_BUFFERS 4
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#define STM32_MAC_BUFFERS_SIZE 1522
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#define STM32_MAC_PHY_TIMEOUT 100
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#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
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#define STM32_MAC_ETH1_IRQ_PRIORITY 13
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#define STM32_MAC_IP_CHECKSUM_OFFLOAD FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM8 FALSE
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#define STM32_PWM_USE_TIM12 FALSE
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#define STM32_PWM_USE_TIM13 FALSE
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#define STM32_PWM_USE_TIM14 FALSE
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#define STM32_PWM_USE_TIM15 FALSE
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#define STM32_PWM_USE_TIM16 FALSE
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#define STM32_PWM_USE_TIM17 FALSE
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/*
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* RTC driver system settings.
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*/
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#define STM32_RTC_PRESA_VALUE 32
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#define STM32_RTC_PRESS_VALUE 1024
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#define STM32_RTC_CR_INIT 0
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#define STM32_TAMP_CR1_INIT 0
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#define STM32_TAMP_CR2_INIT 0
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#define STM32_TAMP_FLTCR_INIT 0
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#define STM32_TAMP_IER_INIT 0
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/*
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* SDC driver system settings.
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*/
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#define STM32_SDC_USE_SDMMC1 FALSE
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#define STM32_SDC_USE_SDMMC2 FALSE
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#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
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#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000
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#define STM32_SDC_SDMMC_READ_TIMEOUT 10000
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#define STM32_SDC_SDMMC_CLOCK_DELAY 10
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#define STM32_SDC_SDMMC_PWRSAV TRUE
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 FALSE
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#define STM32_SERIAL_USE_USART6 FALSE
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#define STM32_SERIAL_USE_UART7 FALSE
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#define STM32_SERIAL_USE_UART8 FALSE
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#define STM32_SERIAL_USE_UART9 FALSE
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#define STM32_SERIAL_USE_USART10 FALSE
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#define STM32_SERIAL_USE_USART11 FALSE
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#define STM32_SERIAL_USE_UART12 FALSE
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#define STM32_SERIAL_USE_LPUART1 FALSE
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/*
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* SIO driver system settings.
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*/
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#define STM32_SIO_USE_USART1 FALSE
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#define STM32_SIO_USE_USART2 FALSE
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#define STM32_SIO_USE_USART3 TRUE
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#define STM32_SIO_USE_UART4 FALSE
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#define STM32_SIO_USE_UART5 FALSE
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#define STM32_SIO_USE_USART6 FALSE
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#define STM32_SIO_USE_UART7 FALSE
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#define STM32_SIO_USE_UART8 FALSE
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#define STM32_SIO_USE_UART9 FALSE
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#define STM32_SIO_USE_USART10 FALSE
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#define STM32_SIO_USE_USART11 FALSE
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#define STM32_SIO_USE_UART12 FALSE
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#define STM32_SIO_USE_LPUART1 FALSE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_USE_SPI4 FALSE
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#define STM32_SPI_USE_SPI5 FALSE
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#define STM32_SPI_USE_SPI6 FALSE
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#define STM32_SPI_SPI1_RX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI1_TX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI2_RX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI2_TX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI3_RX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI3_TX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI4_RX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI4_TX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI5_RX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI5_TX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI6_RX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI6_TX_GPDMA_CHANNEL STM32_GPDMA_MASK_FIFO2
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI5_DMA_PRIORITY 1
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#define STM32_SPI_SPI6_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#define STM32_SPI_SPI6_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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/*
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* TRNG driver system settings.
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*/
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#define STM32_TRNG_USE_RNG1 FALSE
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/*
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* UART driver system settings.
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*/
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_USB1 FALSE
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#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
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#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
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#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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/*
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* WSPI driver system settings.
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*/
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#endif /* MCUCONF_H */
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