mirror of https://github.com/rusefi/ChibiOS.git
194 lines
7.9 KiB
C
194 lines
7.9 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2024 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32G4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef XMCUCONF_H
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#define XMCUCONF_H
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#define __STM32G4xx_XMCUCONF__
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#define __STM32G473_XMCUCONF__
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#define __STM32G483_XMCUCONF__
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#define __STM32G474_XMCUCONF__
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#define __STM32G484_XMCUCONF__
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_CLOCK_DYNAMIC TRUE
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PWR_BOOST TRUE
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#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
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#define STM32_PWR_CR3 (PWR_CR3_EIWF)
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#define STM32_PWR_CR4 (0U)
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#define STM32_PWR_PUCRA (0U)
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#define STM32_PWR_PDCRA (0U)
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#define STM32_PWR_PUCRB (0U)
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#define STM32_PWR_PDCRB (0U)
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#define STM32_PWR_PUCRC (0U)
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#define STM32_PWR_PDCRC (0U)
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#define STM32_PWR_PUCRD (0U)
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#define STM32_PWR_PDCRD (0U)
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#define STM32_PWR_PUCRE (0U)
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#define STM32_PWR_PDCRE (0U)
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#define STM32_PWR_PUCRF (0U)
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#define STM32_PWR_PDCRF (0U)
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#define STM32_PWR_PUCRG (0U)
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#define STM32_PWR_PDCRG (0U)
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_SW STM32_SW_PLLRCLK
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 6
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#define STM32_PLLN_VALUE 85
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#define STM32_PLLPDIV_VALUE 0
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#define STM32_PLLP_VALUE 7
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#define STM32_PLLQ_VALUE 8
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#define STM32_PLLR_VALUE 2
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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/*
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* Peripherals clock sources.
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*/
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
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#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
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#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
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#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
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#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
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#define STM32_FDCANSEL STM32_FDCANSEL_HSE
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#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
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#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
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#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
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#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI164041_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 6
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI212229_PRIORITY 6
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#define STM32_IRQ_EXTI30_32_PRIORITY 6
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#define STM32_IRQ_EXTI33_PRIORITY 6
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#define STM32_IRQ_FDCAN1_PRIORITY 10
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#define STM32_IRQ_FDCAN2_PRIORITY 10
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#define STM32_IRQ_FDCAN3_PRIORITY 10
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#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_TIM8_UP_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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#define STM32_IRQ_TIM20_UP_PRIORITY 7
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#define STM32_IRQ_TIM20_CC_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART3_PRIORITY 12
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#define STM32_IRQ_UART4_PRIORITY 12
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#define STM32_IRQ_UART5_PRIORITY 12
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#define STM32_IRQ_LPUART1_PRIORITY 12
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/*
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* SIO driver system settings.
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*/
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#define STM32_SIO_USE_USART1 TRUE
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#define STM32_SIO_USE_USART2 FALSE
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#define STM32_SIO_USE_USART3 FALSE
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#define STM32_SIO_USE_UART4 FALSE
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#define STM32_SIO_USE_UART5 FALSE
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#define STM32_SIO_USE_LPUART1 TRUE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 TRUE
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#define STM32_SPI_USE_SPI3 TRUE
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#define STM32_SPI_USE_SPI4 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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#endif /* XMCUCONF_H */
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