mirror of https://github.com/rusefi/ChibiOS.git
338 lines
10 KiB
C
338 lines
10 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F0xx/adc_lld.h
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* @brief STM32F0xx ADC subsystem low level driver header.
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*
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* @addtogroup ADC
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* @{
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*/
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#ifndef _ADC_LLD_H_
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#define _ADC_LLD_H_
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Sampling rates
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* @{
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*/
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#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
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#define ADC_SMPR_SMP_7P5 1 /**< @brief 21 cycles conversion time. */
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#define ADC_SMPR_SMP_13P5 2 /**< @brief 28 cycles conversion time. */
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#define ADC_SMPR_SMP_28P5 3 /**< @brief 41 cycles conversion time. */
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#define ADC_SMPR_SMP_41P5 4 /**< @brief 54 cycles conversion time. */
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#define ADC_SMPR_SMP_55P5 5 /**< @brief 68 cycles conversion time. */
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#define ADC_SMPR_SMP_71P5 6 /**< @brief 84 cycles conversion time. */
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#define ADC_SMPR_SMP_239P5 7 /**< @brief 252 cycles conversion time. */
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/** @} */
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/**
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* @name Resolution
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* @{
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*/
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#define ADC_CFGR1_RES_12BIT (0 << 3)
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#define ADC_CFGR1_RES_10BIT (1 << 3)
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#define ADC_CFGR1_RES_8BIT (2 << 3)
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#define ADC_CFGR1_RES_6BIT (3 << 3)
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/** @} */
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/**
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* @name Threashold register initializer
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* @{
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*/
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#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief ADC1 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC1 FALSE
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#endif
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/**
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* @brief ADC1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#endif
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/**
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* @brief ADC interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC1 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
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#error "ADC1 not present in the selected device"
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#endif
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#if !STM32_ADC_USE_ADC1
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC1"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC1 DMA"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to ADC1"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADC sample data type.
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*/
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typedef uint16_t adcsample_t;
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/**
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* @brief Channels number in a conversion group.
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*/
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typedef uint16_t adc_channels_num_t;
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/**
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* @brief Possible ADC failure causes.
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* @note Error codes are architecture dependent and should not relied
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* upon.
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*/
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typedef enum {
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ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
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ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
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ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
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} adcerror_t;
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/**
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* @brief Type of a structure representing an ADC driver.
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*/
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typedef struct ADCDriver ADCDriver;
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/**
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* @brief ADC notification callback type.
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*
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* @param[in] adcp pointer to the @p ADCDriver object triggering the
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* callback
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* @param[in] buffer pointer to the most recent samples data
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* @param[in] n number of buffer rows available starting from @p buffer
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*/
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typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
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/**
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* @brief ADC error callback type.
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*
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* @param[in] adcp pointer to the @p ADCDriver object triggering the
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* callback
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* @param[in] err ADC error code
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*/
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typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
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/**
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* @brief Conversion group configuration structure.
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* @details This implementation-dependent structure describes a conversion
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* operation.
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* @note The use of this configuration structure requires knowledge of
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* STM32 ADC cell registers interface, please refer to the STM32
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* reference manual for details.
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*/
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typedef struct {
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/**
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* @brief Enables the circular buffer mode for the group.
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*/
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bool_t circular;
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/**
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* @brief Number of the analog channels belonging to the conversion group.
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*/
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adc_channels_num_t num_channels;
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/**
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* @brief Callback function associated to the group or @p NULL.
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*/
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adccallback_t end_cb;
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/**
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* @brief Error callback or @p NULL.
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*/
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adcerrorcallback_t error_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief ADC CFGR1 register initialization data.
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*/
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uint32_t cfgr1;
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/**
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* @brief ADC TR register initialization data.
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*/
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uint32_t tr;
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/**
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* @brief ADC SMPR register initialization data.
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*/
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uint32_t smpr;
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/**
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* @brief ADC CHSELR register initialization data.
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* @details The number of bits at logic level one in this register must
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* be equal to the number in the @p num_channels field.
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*/
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uint32_t chselr;
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} ADCConversionGroup;
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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uint32_t dummy;
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} ADCConfig;
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/**
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* @brief Structure representing an ADC driver.
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*/
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struct ADCDriver {
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/**
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* @brief Driver state.
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*/
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adcstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const ADCConfig *config;
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/**
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* @brief Current samples buffer pointer or @p NULL.
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*/
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adcsample_t *samples;
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/**
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* @brief Current samples buffer depth or @p 0.
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*/
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size_t depth;
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/**
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* @brief Current conversion group pointer or @p NULL.
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*/
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const ADCConversionGroup *grpp;
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#if ADC_USE_WAIT || defined(__DOXYGEN__)
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/**
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* @brief Waiting thread.
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*/
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Thread *thread;
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#endif
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#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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#if CH_USE_MUTEXES || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the peripheral.
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*/
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Mutex mutex;
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#elif CH_USE_SEMAPHORES
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Semaphore semaphore;
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#endif
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#endif /* ADC_USE_MUTUAL_EXCLUSION */
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#if defined(ADC_DRIVER_EXT_FIELDS)
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ADC_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the ADCx registers block.
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*/
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ADC_TypeDef *adc;
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/**
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* @brief Pointer to associated SMA channel.
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*/
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const stm32_dma_stream_t *dmastp;
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/**
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* @brief DMA mode bit mask.
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*/
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uint32_t dmamode;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Changes the value of the ADC CCR register.
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* @details Use this function in order to enable or disable the internal
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* analog sources. See the documentation in the STM32F0xx Reference
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* Manual.
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*/
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#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
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extern ADCDriver ADCD1;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void adc_lld_init(void);
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void adc_lld_start(ADCDriver *adcp);
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void adc_lld_stop(ADCDriver *adcp);
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void adc_lld_start_conversion(ADCDriver *adcp);
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void adc_lld_stop_conversion(ADCDriver *adcp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_ADC */
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#endif /* _ADC_LLD_H_ */
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/** @} */
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