mirror of https://github.com/rusefi/ChibiOS.git
574 lines
20 KiB
C
574 lines
20 KiB
C
/*
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ChibiOS - Copyright (C) 2016 Rocco Marco Guglielmi
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file l3gd20.h
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* @brief L3GD20 MEMS interface module header.
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*
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* @addtogroup L3GD20
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* @ingroup EX_ST
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* @{
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*/
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#ifndef _L3GD20_H_
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#define _L3GD20_H_
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#include "hal_gyroscope.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Version identification
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* @{
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*/
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/**
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* @brief L3GD20 driver version string.
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*/
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#define EX_L3GD20_VERSION "1.0.5"
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/**
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* @brief L3GD20 driver version major number.
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*/
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#define EX_L3GD20_MAJOR 1
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/**
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* @brief L3GD20 driver version minor number.
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*/
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#define EX_L3GD20_MINOR 0
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/**
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* @brief L3GD20 driver version patch number.
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*/
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#define EX_L3GD20_PATCH 5
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/** @} */
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/**
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* @brief L3GD20 characteristics.
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*
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* @{
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*/
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#define L3GD20_NUMBER_OF_AXES 3U
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#define L3GD20_250DPS 250.0f
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#define L3GD20_500DPS 500.0f
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#define L3GD20_2000DPS 2000.0f
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#define L3GD20_SENS_250DPS 0.00875f
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#define L3GD20_SENS_500DPS 0.01750f
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#define L3GD20_SENS_2000DPS 0.07000f
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/** @} */
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/**
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* @name L3GD20 communication interfaces related bit masks
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* @{
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*/
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#define L3GD20_DI_MASK 0xFF
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#define L3GD20_DI(n) (1 << n)
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#define L3GD20_AD_MASK 0x3F
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#define L3GD20_AD(n) (1 << n)
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#define L3GD20_MS (1 << 6)
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#define L3GD20_RW (1 << 7)
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/** @} */
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/**
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* @name L3GD20 register addresses
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* @{
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*/
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#define L3GD20_AD_WHO_AM_I 0x0F
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#define L3GD20_AD_CTRL_REG1 0x20
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#define L3GD20_AD_CTRL_REG2 0x21
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#define L3GD20_AD_CTRL_REG3 0x22
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#define L3GD20_AD_CTRL_REG4 0x23
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#define L3GD20_AD_CTRL_REG5 0x24
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#define L3GD20_AD_REFERENCE 0x25
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#define L3GD20_AD_OUT_TEMP 0x26
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#define L3GD20_AD_STATUS_REG 0x27
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#define L3GD20_AD_OUT_X_L 0x28
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#define L3GD20_AD_OUT_X_H 0x29
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#define L3GD20_AD_OUT_Y_L 0x2A
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#define L3GD20_AD_OUT_Y_H 0x2B
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#define L3GD20_AD_OUT_Z_L 0x2C
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#define L3GD20_AD_OUT_Z_H 0x2D
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#define L3GD20_AD_FIFO_CTRL_REG 0x2E
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#define L3GD20_AD_FIFO_SRC_REG 0x2F
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#define L3GD20_AD_INT1_CFG 0x30
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#define L3GD20_AD_INT1_SRC 0x31
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#define L3GD20_AD_INT1_THS_XH 0x32
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#define L3GD20_AD_INT1_THS_XL 0x33
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#define L3GD20_AD_INT1_THS_YH 0x34
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#define L3GD20_AD_INT1_THS_YL 0x35
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#define L3GD20_AD_INT1_THS_ZH 0x36
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#define L3GD20_AD_INT1_THS_ZL 0x37
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#define L3GD20_AD_INT1_DURATION 0x38
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/** @} */
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/**
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* @name L3GD20_CTRL_REG1 register bits definitions
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* @{
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*/
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#define L3GD20_CTRL_REG1_MASK 0xFF /**< L3GD20_CTRL_REG1 mask */
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#define L3GD20_CTRL_REG1_XEN (1 << 0) /**< X axis enable */
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#define L3GD20_CTRL_REG1_YEN (1 << 1) /**< Y axis enable */
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#define L3GD20_CTRL_REG1_ZEN (1 << 2) /**< Z axis enable */
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#define L3GD20_CTRL_REG1_PD (1 << 3) /**< Power-down mode enable */
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#define L3GD20_CTRL_REG1_BW0 (1 << 4) /**< Bandwidth bit 0 */
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#define L3GD20_CTRL_REG1_BW1 (1 << 5) /**< Bandwidth bit 1 */
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#define L3GD20_CTRL_REG1_DR0 (1 << 6) /**< Output data rate bit 0 */
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#define L3GD20_CTRL_REG1_DR1 (1 << 7) /**< Output data rate bit 1 */
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/** @} */
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/**
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* @name L3GD20_CTRL_REG2 register bits definitions
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* @{
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*/
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#define L3GD20_CTRL_REG2_MASK 0x3F /**< L3GD20_CTRL_REG2 mask */
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#define L3GD20_CTRL_REG2_HPCF0 (1 << 0) /**< HP filter cutoff bit 0 */
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#define L3GD20_CTRL_REG2_HPCF1 (1 << 1) /**< HP filter cutoff bit 1 */
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#define L3GD20_CTRL_REG2_HPCF2 (1 << 2) /**< HP filter cutoff bit 2 */
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#define L3GD20_CTRL_REG2_HPCF3 (1 << 3) /**< HP filter cutoff bit 3 */
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#define L3GD20_CTRL_REG2_HPM0 (1 << 4) /**< HP filter mode bit 0 */
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#define L3GD20_CTRL_REG2_HPM1 (1 << 5) /**< HP filter mode bit 1 */
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/** @} */
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/**
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* @name L3GD20_CTRL_REG3 register bits definitions
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* @{
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*/
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#define L3GD20_CTRL_REG3_MASK 0xFF /**< L3GD20_CTRL_REG3 mask */
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#define L3GD20_CTRL_REG3_I2_EMPTY (1 << 0) /**< FIFO empty IRQ */
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#define L3GD20_CTRL_REG3_I2_ORUN (1 << 1) /**< FIFO overrun IRQ */
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#define L3GD20_CTRL_REG3_I2_WTM (1 << 2) /**< FIFO watermark IRQ */
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#define L3GD20_CTRL_REG3_I2_DRDY (1 << 3) /**< Data ready */
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#define L3GD20_CTRL_REG3_PP_OD (1 << 4) /**< Push-pull / Open Drain */
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#define L3GD20_CTRL_REG3_H_LACTIVE (1 << 5) /**< IRQ active */
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#define L3GD20_CTRL_REG3_I1_BOOT (1 << 6) /**< Boot status available */
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#define L3GD20_CTRL_REG3_I1_INT1 (1 << 7) /**< IRQ enable */
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/** @} */
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/**
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* @name L3GD20_CTRL_REG4 register bits definitions
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* @{
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*/
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#define L3GD20_CTRL_REG4_MASK 0xF1 /**< L3GD20_CTRL_REG4 mask */
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#define L3GD20_CTRL_REG4_SIM (1 << 0) /**< SPI mode */
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#define L3GD20_CTRL_REG4_FS_MASK 0x30 /**< Full scale field mask */
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#define L3GD20_CTRL_REG4_FS0 (1 << 4) /**< Full scale bit 0 */
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#define L3GD20_CTRL_REG4_FS1 (1 << 5) /**< Full scale bit 1 */
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#define L3GD20_CTRL_REG4_BLE (1 << 6) /**< Big/little endian data */
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#define L3GD20_CTRL_REG4_BDU (1 << 7) /**< Block data update */
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/** @} */
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/**
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* @name L3GD20_CTRL_REG5 register bits definitions
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* @{
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*/
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#define L3GD20_CTRL_REG5_MASK 0xDF /**< L3GD20_CTRL_REG5 mask */
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#define L3GD20_CTRL_REG5_OUT_SEL0 (1 << 0) /**< Out selection bit 0 */
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#define L3GD20_CTRL_REG5_OUT_SEL1 (1 << 1) /**< Out selection bit 1 */
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#define L3GD20_CTRL_REG5_INT1_SEL0 (1 << 2) /**< INT1 selection bit 0 */
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#define L3GD20_CTRL_REG5_INT1_SEL1 (1 << 3) /**< INT1 selection bit 1 */
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#define L3GD20_CTRL_REG5_HPEN (1 << 4) /**< HP filter enable */
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#define L3GD20_CTRL_REG5_FIFO_EN (1 << 6) /**< FIFO enable */
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#define L3GD20_CTRL_REG5_BOOT (1 << 7) /**< Reboot memory content */
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/** @} */
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/**
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* @name L3GD20_INT1_CFG register bits definitions
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* @{
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*/
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#define L3GD20_INT1_CFG_MASK 0xFF /**< L3GD20_INT1_CFG mask */
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#define L3GD20_INT1_CFG_XLIE (1 << 0) /**< Enable INT1 on X low */
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#define L3GD20_INT1_CFG_XHIE (1 << 1) /**< Enable INT1 on X high */
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#define L3GD20_INT1_CFG_YLIE (1 << 2) /**< Enable INT1 on Y low */
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#define L3GD20_INT1_CFG_YHIE (1 << 3) /**< Enable INT1 on Y high */
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#define L3GD20_INT1_CFG_ZLIE (1 << 4) /**< Enable INT1 on Z low */
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#define L3GD20_INT1_CFG_ZHIE (1 << 5) /**< Enable INT1 on Z high */
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#define L3GD20_INT1_CFG_LIR (1 << 6) /**< Latch INT1 */
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#define L3GD20_INT1_CFG_AND_OR (1 << 7) /**< AND OR combination */
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/** @} */
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/**
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* @name L3GD20_INT1_SRC register bits definitions
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* @{
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*/
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#define L3GD20_INT1_SRC_MASK 0x7F /**< L3GD20_INT1_SRC mask */
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#define L3GD20_INT1_SRC_XL (1 << 0) /**< X low event */
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#define L3GD20_INT1_SRC_XH (1 << 1) /**< X high event */
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#define L3GD20_INT1_SRC_YL (1 << 2) /**< Y low event */
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#define L3GD20_INT1_SRC_YH (1 << 3) /**< Y high event */
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#define L3GD20_INT1_SRC_ZL (1 << 4) /**< Z low event */
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#define L3GD20_INT1_SRC_ZH (1 << 5) /**< Z high event */
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#define L3GD20_INT1_SRC_IA (1 << 6) /**< Interrupt active */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief L3GD20 SPI interface switch.
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* @details If set to @p TRUE the support for SPI is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(L3GD20_USE_SPI) || defined(__DOXYGEN__)
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#define L3GD20_USE_SPI TRUE
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#endif
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/**
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* @brief L3GD20 I2C interface switch.
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* @details If set to @p TRUE the support for I2C is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(L3GD20_USE_I2C) || defined(__DOXYGEN__)
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#define L3GD20_USE_I2C FALSE
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#endif
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/**
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* @brief L3GD20 advanced configurations switch.
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* @details If set to @p TRUE more configurations are available.
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* @note The default is @p FALSE.
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*/
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#if !defined(L3GD20_USE_ADVANCED) || defined(__DOXYGEN__)
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#define L3GD20_USE_ADVANCED FALSE
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#endif
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/**
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* @brief L3GD20 shared SPI switch.
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* @details If set to @p TRUE the device acquires SPI bus ownership
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* on each transaction.
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* @note The default is @p FALSE. Requires SPI_USE_MUTUAL_EXCLUSION
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*/
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#if !defined(L3GD20_SHARED_SPI) || defined(__DOXYGEN__)
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#define L3GD20_SHARED_SPI FALSE
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#endif
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/**
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* @brief Number of acquisitions for bias removal
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* @details This is the number of acquisitions performed to compute the
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* bias. A repetition is required in order to remove noise.
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*/
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#if !defined(L3GD20_BIAS_ACQ_TIMES) || defined(__DOXYGEN__)
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#define L3GD20_BIAS_ACQ_TIMES 50
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#endif
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/**
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* @brief Settling time for bias removal
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* @details This is the time between each bias acquisition.
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*/
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#if !defined(L3GD20_BIAS_SETTLING_uS) || defined(__DOXYGEN__)
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#define L3GD20_BIAS_SETTLING_uS 5000
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !(L3GD20_USE_SPI ^ L3GD20_USE_I2C)
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#error "L3GD20_USE_SPI and L3GD20_USE_I2C cannot be both true or both false"
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#endif
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#if L3GD20_USE_SPI && !HAL_USE_SPI
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#error "L3GD20_USE_SPI requires HAL_USE_SPI"
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#endif
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//TODO: add I2C support.
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#if L3GD20_USE_I2C
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#error "L3GD20 over I2C still not supported"
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#endif
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#if L3GD20_USE_I2C && !HAL_USE_I2C
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#error "L3GD20_USE_I2C requires HAL_USE_I2C"
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#endif
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#if L3GD20_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION
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#error "L3GD20_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @name L3GD20 data structures and types.
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* @{
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*/
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/**
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* @brief L3GD20 full scale.
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*/
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typedef enum {
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L3GD20_FS_250DPS = 0x00, /**< Full scale 250 degree per second. */
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L3GD20_FS_500DPS = 0x10, /**< Full scale 500 degree per second. */
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L3GD20_FS_2000DPS = 0x20 /**< Full scale 2000 degree per second. */
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}l3gd20_fs_t;
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/**
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* @brief L3GD20 output data rate and bandwidth.
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*/
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typedef enum {
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L3GD20_ODR_95HZ = 0x00, /**< Output data rate 95 Hz. */
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L3GD20_ODR_190HZ = 0x40, /**< Output data rate 190 Hz. */
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L3GD20_ODR_380HZ = 0x80, /**< Output data rate 380 Hz. */
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L3GD20_ODR_760HZ = 0xC0 /**< Output data rate 760 Hz. */
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}l3gd20_odr_t;
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/**
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* @brief L3GD20 low pass filter 1 bandwidth.
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*/
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typedef enum {
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L3GD20_BW0 = 0x00, /**< LPF1 bandwidth. Depends on ODR. */
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L3GD20_BW1 = 0x40, /**< LPF1 bandwidth. Depends on ODR. */
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L3GD20_BW2 = 0x80, /**< LPF1 bandwidth. Depends on ODR. */
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L3GD20_BW3 = 0xC0 /**< LPF1 bandwidth. Depends on ODR. */
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}l3gd20_bw_t;
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/**
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* @brief L3GD20 block data update.
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*/
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typedef enum {
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L3GD20_BDU_CONTINUOUS = 0x00, /**< Block data continuously updated. */
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L3GD20_BDU_BLOCKED = 0x80 /**< Block data updated after reading. */
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}l3gd20_bdu_t;
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/**
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* @brief L3GD20 HP filter mode.
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*/
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typedef enum {
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L3GD20_HPM_NORMAL = 0x00, /**< Normal mode. */
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L3GD20_HPM_REFERENCE = 0x10, /**< Reference signal for filtering. */
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L3GD20_HPM_AUTORESET = 0x30, /**< Autoreset on interrupt event. */
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L3GD20_HPM_BYPASSED = 0xFF /**< HP filter bypassed */
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}l3gd20_hpm_t;
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/**
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* @brief L3GD20 HP configuration.
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*/
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typedef enum {
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L3GD20_HPCF_0 = 0x00, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_1 = 0x01, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_2 = 0x02, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_3 = 0x03, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_4 = 0x04, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_5 = 0x05, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_6 = 0x06, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_7 = 0x07, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_8 = 0x08, /**< Depends on ODR (Table 26 for more).*/
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L3GD20_HPCF_9 = 0x09 /**< Depends on ODR (Table 26 for more).*/
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}l3gd20_hpcf_t;
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/**
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* @brief L3GD20 LP2 filter mode.
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* @details To activate LP2 HP should be active
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*/
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typedef enum {
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L3GD20_LP2M_ON = 0x00, /**< LP2 filter activated. */
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L3GD20_LP2M_BYPASSED = 0xFF, /**< LP2 filter bypassed. */
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}l3gd20_lp2m_t;
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/**
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* @brief L3GD20 endianness.
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*/
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typedef enum {
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L3GD20_END_LITTLE = 0x00, /**< Little endian. */
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L3GD20_END_BIG = 0x40 /**< Big endian. */
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}l3gd20_end_t;
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/**
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* @brief Driver state machine possible states.
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*/
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typedef enum {
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L3GD20_UNINIT = 0, /**< Not initialized. */
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L3GD20_STOP = 1, /**< Stopped. */
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L3GD20_READY = 2, /**< Ready. */
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} l3gd20_state_t;
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/**
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* @brief L3GD20 configuration structure.
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*/
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typedef struct {
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#if L3GD20_USE_SPI || defined(__DOXYGEN__)
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/**
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* @brief SPI driver associated to this L3GD20.
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*/
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SPIDriver *spip;
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/**
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* @brief SPI configuration associated to this L3GD20.
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*/
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const SPIConfig *spicfg;
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#endif /* L3GD20_USE_SPI */
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#if L3GD20_USE_I2C || defined(__DOXYGEN__)
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/**
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* @brief I2C driver associated to this L3GD20.
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*/
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I2CDriver *i2cp;
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/**
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* @brief I2C configuration associated to this L3GD20.
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*/
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const I2CConfig *i2ccfg;
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#endif /* L3GD20_USE_I2C */
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/**
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* @brief L3GD20 initial sensitivity.
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*/
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float *sensitivity;
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/**
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|
* @brief L3GD20 initial bias.
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|
*/
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|
float *bias;
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/**
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|
* @brief L3GD20 initial full scale value.
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|
*/
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|
l3gd20_fs_t fullscale;
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|
/**
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|
* @brief L3GD20 output data rate selection.
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|
*/
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|
l3gd20_odr_t outputdatarate;
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|
#if L3GD20_USE_ADVANCED || defined(__DOXYGEN__)
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/**
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|
* @brief L3GD20 block data update.
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|
*/
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|
l3gd20_bdu_t blockdataupdate;
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|
/**
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|
* @brief L3GD20 endianness.
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|
*/
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|
l3gd20_end_t endianness;
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|
/**
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|
* @brief L3GD20 LP1 filter bandwidth.
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|
*/
|
|
l3gd20_bw_t bandwidth;
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|
/**
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|
* @brief L3GD20 HP filter mode.
|
|
*/
|
|
l3gd20_hpm_t hpmode;
|
|
/**
|
|
* @brief L3GD20 HP configuration.
|
|
*/
|
|
l3gd20_hpcf_t hpconfiguration;
|
|
/**
|
|
* @brief L3GD20 LP2 filter mode.
|
|
* @details To activate LP2 HP should be active
|
|
*/
|
|
l3gd20_lp2m_t lp2mode;
|
|
#endif
|
|
} L3GD20Config;
|
|
|
|
/**
|
|
* @brief @p L3GD20 gyroscope subsystem specific methods.
|
|
*/
|
|
#define _l3gd20_gyroscope_methods_alone \
|
|
/* Change full scale value of L3GD20.*/ \
|
|
msg_t (*set_full_scale)(void *instance, l3gd20_fs_t fs);
|
|
|
|
/**
|
|
* @brief @p L3GD20 gyroscope subsystem specific methods with inherited ones.
|
|
*/
|
|
#define _l3gd20_gyroscope_methods \
|
|
_base_gyroscope_methods \
|
|
_l3gd20_gyroscope_methods_alone
|
|
|
|
/**
|
|
* @extends BaseGyroscopeVMT
|
|
*
|
|
* @brief @p L3GD20 gyroscope virtual methods table.
|
|
*/
|
|
struct L3GD20GyroscopeVMT {
|
|
_l3gd20_gyroscope_methods
|
|
};
|
|
|
|
/**
|
|
* @brief @p L3GD20Driver specific data.
|
|
*/
|
|
#define _l3gd20_data \
|
|
_base_gyroscope_data \
|
|
/* Driver state.*/ \
|
|
l3gd20_state_t state; \
|
|
/* Current configuration data.*/ \
|
|
const L3GD20Config *config; \
|
|
/* Current sensitivity data.*/ \
|
|
float sensitivity[L3GD20_NUMBER_OF_AXES]; \
|
|
/* Current Bias data.*/ \
|
|
float bias[L3GD20_NUMBER_OF_AXES]; \
|
|
/* Current full scale value.*/ \
|
|
float fullscale;
|
|
|
|
/**
|
|
* @extends BaseGyroscope
|
|
*
|
|
* @brief L3GD20 3-axis gyroscope class.
|
|
* @details This class extends @p BaseGyroscope by adding physical
|
|
* driver implementation.
|
|
*/
|
|
struct L3GD20Driver {
|
|
/** @brief BaseSensor Virtual Methods Table. */
|
|
const struct BaseSensorVMT *vmt_sensor;
|
|
_base_sensor_data
|
|
/** @brief L3GD20 Gyroscope Virtual Methods Table. */
|
|
const struct L3GD20GyroscopeVMT *vmt_gyroscope;
|
|
_base_gyroscope_data
|
|
_l3gd20_data
|
|
};
|
|
|
|
/**
|
|
* @brief Structure representing a L3GD20 driver.
|
|
*/
|
|
typedef struct L3GD20Driver L3GD20Driver;
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* Driver macros. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @brief Change gyroscope full scale value.
|
|
*
|
|
* @param[in] ip pointer to a @p L3GD20Driver class.
|
|
* @param[in] fs the new full scale value.
|
|
*
|
|
* @return The operation status.
|
|
* @retval MSG_OK if the function succeeded.
|
|
* @retval MSG_RESET if one or more errors occurred.
|
|
* @api
|
|
*/
|
|
#define gyroscopeSetFullScale(ip, fs) \
|
|
(ip)->vmt_gyroscope->set_full_scale(ip, fs)
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
void l3gd20ObjectInit(L3GD20Driver *devp);
|
|
void l3gd20Start(L3GD20Driver *devp, const L3GD20Config *config);
|
|
void l3gd20Stop(L3GD20Driver *devp);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _L3GD20_H_ */
|
|
|
|
/** @} */
|
|
|