mirror of https://github.com/rusefi/ChibiOS.git
256 lines
6.2 KiB
C
256 lines
6.2 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F1xx/stm32_isr.c
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* @brief STM32F1xx ISR handler code.
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*
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* @addtogroup STM32F1xx_ISR
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#define exti_serve_irq(pr, channel) { \
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\
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if ((pr) & (1U << (channel))) { \
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_pal_isr_code(channel); \
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} \
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
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#if !defined(STM32_DISABLE_EXTI0_HANDLER)
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/**
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* @brief EXTI[0] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector58) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 0);
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EXTI->PR = pr;
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exti_serve_irq(pr, 0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI1_HANDLER)
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/**
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* @brief EXTI[1] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector5C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 1);
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EXTI->PR = pr;
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exti_serve_irq(pr, 1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI2_HANDLER)
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/**
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* @brief EXTI[2] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector60) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 2);
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EXTI->PR = pr;
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exti_serve_irq(pr, 2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI3_HANDLER)
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/**
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* @brief EXTI[3] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector64) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 3);
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EXTI->PR = pr;
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exti_serve_irq(pr, 3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI4_HANDLER)
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/**
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* @brief EXTI[4] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector68) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & (1U << 4);
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EXTI->PR = pr;
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exti_serve_irq(pr, 4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
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/**
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* @brief EXTI[5]...EXTI[9] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector9C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
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(1U << 9));
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EXTI->PR = pr;
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exti_serve_irq(pr, 5);
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exti_serve_irq(pr, 6);
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exti_serve_irq(pr, 7);
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exti_serve_irq(pr, 8);
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exti_serve_irq(pr, 9);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
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/**
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* @brief EXTI[10]...EXTI[15] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorE0) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR;
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pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
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(1U << 14) | (1U << 15));
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EXTI->PR = pr;
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exti_serve_irq(pr, 10);
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exti_serve_irq(pr, 11);
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exti_serve_irq(pr, 12);
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exti_serve_irq(pr, 13);
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exti_serve_irq(pr, 14);
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exti_serve_irq(pr, 15);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#endif /* HAL_USE_PAL */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Enables IRQ sources.
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*
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* @notapi
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*/
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void irqInit(void) {
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#if HAL_USE_PAL
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nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
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nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
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nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
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nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
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nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
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nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
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nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
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#endif
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}
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/**
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* @brief Disables IRQ sources.
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*
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* @notapi
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*/
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void irqDeinit(void) {
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#if HAL_USE_PAL
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nvicDisableVector(EXTI0_IRQn);
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nvicDisableVector(EXTI1_IRQn);
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nvicDisableVector(EXTI2_IRQn);
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nvicDisableVector(EXTI3_IRQn);
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nvicDisableVector(EXTI4_IRQn);
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nvicDisableVector(EXTI9_5_IRQn);
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nvicDisableVector(EXTI15_10_IRQn);
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#endif
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}
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/** @} */
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