mirror of https://github.com/rusefi/ChibiOS.git
1022 lines
22 KiB
C
1022 lines
22 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F37x/stm32_rcc.h
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* @brief RCC helper driver header.
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* @note This file requires definitions from the ST header file
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* @p stm32f30x.h.
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*
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* @addtogroup STM32F37x_RCC
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* @{
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*/
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#ifndef STM32_RCC_H
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#define STM32_RCC_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Generic RCC operations
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* @{
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*/
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/**
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* @brief Enables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB1(mask, lp) { \
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RCC->APB1ENR |= (mask); \
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(void)RCC->APB1ENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB1(mask) { \
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RCC->APB1ENR &= ~(mask); \
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(void)RCC->APB1ENR; \
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}
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/**
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* @brief Resets one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB1(mask) { \
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RCC->APB1RSTR |= (mask); \
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RCC->APB1RSTR &= ~(mask); \
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(void)RCC->APB1RSTR; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB2(mask, lp) { \
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RCC->APB2ENR |= (mask); \
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(void)RCC->APB2ENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccDisableAPB2(mask) { \
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RCC->APB2ENR &= ~(mask); \
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(void)RCC->APB2ENR; \
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}
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/**
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* @brief Resets one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB2(mask) { \
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RCC->APB2RSTR |= (mask); \
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RCC->APB2RSTR &= ~(mask); \
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(void)RCC->APB2RSTR; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB bus.
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*
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* @param[in] mask AHB peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB(mask, lp) { \
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RCC->AHBENR |= (mask); \
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(void)RCC->AHBENR; \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB bus.
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*
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* @param[in] mask AHB peripherals mask
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*
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* @api
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*/
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#define rccDisableAHB(mask) { \
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RCC->AHBENR &= ~(mask); \
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(void)RCC->AHBENR; \
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}
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/**
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* @brief Resets one or more peripheral on the AHB bus.
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*
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* @param[in] mask AHB peripherals mask
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*
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* @api
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*/
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#define rccResetAHB(mask) { \
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RCC->AHBRSTR |= (mask); \
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RCC->AHBRSTR &= ~(mask); \
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(void)RCC->AHBRSTR; \
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}
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/** @} */
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/**
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* @name ADC1 peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the ADC peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
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/**
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* @brief Disables the ADC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
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/**
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* @brief Resets the ADC1 peripheral.
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*
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* @api
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*/
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#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
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/** @} */
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/**
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* @name DAC peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DAC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
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/**
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* @brief Disables the DAC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DAC1EN)
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/**
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* @brief Resets the DAC1 peripheral.
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*
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* @api
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*/
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#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
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/**
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* @brief Enables the DAC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
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/**
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* @brief Disables the DAC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC2() rccDisableAPB1(RCC_APB1ENR_DAC2EN)
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/**
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* @brief Resets the DAC1 peripheral.
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*
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* @api
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*/
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#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
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/** @} */
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/**
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* @name CAN peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the CAN1 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
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/**
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* @brief Disables the CAN1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CANEN)
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/**
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* @brief Resets the CAN1 peripheral.
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*
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* @api
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*/
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#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
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/** @} */
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/**
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* @name DMA peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DMA1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
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/**
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* @brief Disables the DMA1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
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/**
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* @brief Resets the DMA1 peripheral.
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*
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* @api
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*/
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#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
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/**
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* @brief Enables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
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/**
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* @brief Disables the DMA2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN)
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/**
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* @brief Resets the DMA2 peripheral.
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*
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* @api
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*/
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#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
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/** @} */
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/**
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* @name PWR interface specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the PWR interface clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
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/**
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* @brief Disables PWR interface clock.
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*
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* @api
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*/
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#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
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/**
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* @brief Resets the PWR interface.
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*
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* @api
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*/
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#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
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/** @} */
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/**
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* @name I2C peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the I2C1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
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/**
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* @brief Disables the I2C1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
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/**
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* @brief Resets the I2C1 peripheral.
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*
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* @api
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*/
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#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
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/**
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* @brief Enables the I2C2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
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/**
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* @brief Disables the I2C2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
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/**
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* @brief Resets the I2C2 peripheral.
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*
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* @api
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*/
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#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
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/** @} */
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/**
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* @name SDADC peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the SDADC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSDADC1(lp) rccEnableAPB2(RCC_APB2ENR_SDADC1EN, lp)
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/**
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* @brief Disables the SDADC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSDADC1() rccDisableAPB2(RCC_APB2ENR_SDADC1EN)
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/**
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* @brief Resets the SDADC1 peripheral.
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*
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* @api
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*/
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#define rccResetSDADC1() rccResetAPB2(RCC_APB2RSTR_SDADC1RST)
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/**
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* @brief Enables the SDADC2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSDADC2(lp) rccEnableAPB2(RCC_APB2ENR_SDADC2EN, lp)
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/**
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* @brief Disables the SDADC2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSDADC2() rccDisableAPB2(RCC_APB2ENR_SDADC2EN)
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/**
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* @brief Resets the SDADC2 peripheral.
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*
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* @api
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*/
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#define rccResetSDADC2() rccResetAPB2(RCC_APB2RSTR_SDADC2RST)
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/**
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* @brief Enables the SDADC3 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSDADC3(lp) rccEnableAPB2(RCC_APB2ENR_SDADC3EN, lp)
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/**
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* @brief Disables the SDADC3 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSDADC3() rccDisableAPB2(RCC_APB2ENR_SDADC3EN)
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/**
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* @brief Resets the SDADC3 peripheral.
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*
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* @api
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*/
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#define rccResetSDADC3() rccResetAPB2(RCC_APB2RSTR_SDADC3RST)
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/** @} */
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/**
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* @name SPI peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the SPI1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
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/**
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* @brief Disables the SPI1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
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/**
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* @brief Resets the SPI1 peripheral.
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*
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* @api
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*/
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#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
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/**
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* @brief Enables the SPI2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
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/**
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* @brief Disables the SPI2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
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/**
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* @brief Resets the SPI2 peripheral.
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*
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* @api
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*/
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#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
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/**
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* @brief Enables the SPI3 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
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/**
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* @brief Disables the SPI3 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSPI3() rccDisableAPB1(RCC_APB1ENR_SPI3EN)
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/**
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* @brief Resets the SPI3 peripheral.
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*
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* @api
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*/
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#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
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/** @} */
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/**
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* @name TIM peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the TIM2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
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/**
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* @brief Disables the TIM2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
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/**
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* @brief Resets the TIM2 peripheral.
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*
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* @api
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|
*/
|
|
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM3 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM3 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM3 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM4 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM4 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM4 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM5 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM5 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM5() rccDisableAPB1(RCC_APB1ENR_TIM5EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM5 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM6 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM6 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM6 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM7 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM7 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM7 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM12 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM12 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM12() rccDisableAPB1(RCC_APB1ENR_TIM12EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM12 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM13 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM13 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM13() rccDisableAPB1(RCC_APB1ENR_TIM13EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM13 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
|
|
|
|
|
|
/**
|
|
* @brief Enables the TIM14 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM14 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM14 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM15 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM15 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM15 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM16 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM16 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM16 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM17 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM17 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM17 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM18 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM18(lp) rccEnableAPB1(RCC_APB1ENR_TIM18EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM18 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM18() rccDisableAPB1(RCC_APB1ENR_TIM18EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM18 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM18() rccResetAPB1(RCC_APB1RSTR_TIM18RST)
|
|
|
|
/**
|
|
* @brief Enables the TIM19 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableTIM19(lp) rccEnableAPB2(RCC_APB2ENR_TIM19EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the TIM19 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableTIM19() rccDisableAPB2(RCC_APB2ENR_TIM19EN)
|
|
|
|
/**
|
|
* @brief Resets the TIM19 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetTIM19() rccResetAPB2(RCC_APB2RSTR_TIM19RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name USART/UART peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the USART1 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART1 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
|
|
|
|
/**
|
|
* @brief Resets the USART1 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
|
|
|
|
/**
|
|
* @brief Enables the USART2 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART2 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
|
|
|
|
/**
|
|
* @brief Resets the USART2 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
|
|
|
|
/**
|
|
* @brief Enables the USART3 peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USART3 peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
|
|
|
|
/**
|
|
* @brief Resets the USART3 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name USB peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the USB peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USB peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSB() rccDisableAPB1(RCC_APB1ENR_USBEN)
|
|
|
|
/**
|
|
* @brief Resets the USB peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name CRC peripherals specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the CRC peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the CRC peripheral clock.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32_RCC_H */
|
|
|
|
/** @} */
|