mirror of https://github.com/rusefi/ChibiOS.git
41 lines
1.3 KiB
C
Executable File
41 lines
1.3 KiB
C
Executable File
#include "ch.h"
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#include "hal.h"
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/*
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* @brief Fragment to turn execution into non-secure mode
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*/
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void go2ns(void) {
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/* Configure SRAM0 as not secure Read and not secure write */
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mtxConfigSlaveSec(MATRIX0,H64MX_SLAVE_SRAM, LOWER_AREA_SECURABLE,
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NOT_SECURE_READ, NOT_SECURE_WRITE);
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/* Configure SRAM0 upper area as not secure Read and secure write */
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mtxConfigSlaveSec(MATRIX0, H64MX_SLAVE_SRAM, UPPER_AREA_SECURABLE,
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NOT_SECURE_READ, SECURE_WRITE);
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asm(
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"mrc p15, 0, r0, c1, c1, 0\n\t" /* Set NS bit into SCR register */
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"orr r0, r0, #1\n\t" /* bit 0 is the NS bit */
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"mcr p15, 0, r0, c1, c1, 0\n\t"
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);
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}
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/*
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* Application entry point.
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*/
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int main(void) {
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/* SRAM1 split at 64K */
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mtxSetSlaveSplitAddr(MATRIX0, H64MX_SLAVE_L2C_SRAM, MATRIX_AREA_SIZE_64K,
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REGION_0);
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uint32_t *writeNotSecureSRAM1 = (uint32_t *)(0x200000 + 61 * 1024); /* Lower area region SRAM0 */
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uint32_t *writeSecureSRAM1 = (uint32_t *)(0x200000 + 65 * 1024); /* Upper area region SRAM0 */
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/* Go into Not Secure Mode*/
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go2ns();
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/* Writing in SRAM0 Lower Area */
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*writeNotSecureSRAM1 = 0xAA55AA55; /* writing succeeded*/
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/* Writing in SRAM0 Upper Area */
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*writeSecureSRAM1 = 0xAA55AA55; /* writing not succeeded*/
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while (true) {
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;
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}
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}
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