mirror of https://github.com/rusefi/ChibiOS.git
113 lines
3.5 KiB
C
113 lines
3.5 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include <nvic.h>
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#include "board.h"
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#include "stm32_serial.h"
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/*
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* Early initialization code.
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* This initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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void hwinit0(void) {
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/*
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* Clocks and PLL initialization.
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*/
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// HSI setup.
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RCC->CR = HSITRIM_RESET_BITS | CR_HSION_MASK;
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while (!(RCC->CR & CR_HSIRDY_MASK))
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; // Waits until HSI stable, it should already be.
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// HSE setup.
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RCC->CR |= CR_HSEON_MASK;
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while (!(RCC->CR & CR_HSERDY_MASK))
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; // Waits until HSE stable.
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// PLL setup.
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RCC->CFGR = PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
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RCC->CR |= CR_PLLON_MASK;
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while (!(RCC->CR & CR_PLLRDY_MASK))
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; // Waits until PLL stable.
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// Clock sources.
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RCC->CFGR |= HPRE_DIV1_BITS | PPRE1_DIV2_BITS | PPRE2_DIV2_BITS |
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ADCPRE_DIV8_BITS | USBPREBITS | MCO_DISABLED_BITS;
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/*
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* Flash setup and final clock selection.
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*/
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FLASH->ACR = FLASHBITS; // Flash wait states depending on clock.
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RCC->CFGR |= SW_PLL_BITS; // Switches on the PLL clock.
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while ((RCC->CFGR & CFGR_SWS_MASK) != SWS_PLL_BITS)
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;
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/*
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* I/O ports initialization as specified in board.h. Note that being this
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* a low level initialization routine it is OK to invoke directly the
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* low level port functions.
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*/
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ioport_init_lld();
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ioport_stm32_setup_lld(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL);
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ioport_write_lld(IOPORT_A, VAL_GPIOAODR);
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ioport_stm32_setup_lld(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL);
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ioport_write_lld(IOPORT_B, VAL_GPIOBODR);
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ioport_stm32_setup_lld(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL);
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ioport_write_lld(IOPORT_C, VAL_GPIOCODR);
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ioport_stm32_setup_lld(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL);
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ioport_write_lld(IOPORT_D, VAL_GPIODODR);
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}
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/*
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* Late initialization code.
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* This initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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void hwinit1(void) {
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/*
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* NVIC/SCB initialization.
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*/
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4).
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NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
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NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
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/*
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* SysTick initialization.
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*/
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ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
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ST_CVR = 0;
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ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS;
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/*
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* Other subsystems initialization.
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*/
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serial_init(0xC0, 0xC0, 0xC0);
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/*
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* ChibiOS/RT initialization.
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*/
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chSysInit();
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}
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