mirror of https://github.com/rusefi/ChibiOS.git
120 lines
3.9 KiB
Plaintext
120 lines
3.9 KiB
Plaintext
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @defgroup STM8S STM8S Drivers
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* @details This section describes all the supported drivers on the STM8S
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* platform and the implementation details of the single drivers.
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup STM8S_HAL STM8S Initialization Support
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* @details The STM8S HAL support is responsible for system initialization.
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*
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* @section stm8s_hal_1 Supported HW resources
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* - CLK.
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* .
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* @section stm8s_hal_2 STM8S HAL driver implementation features
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* - Clock tree initialization.
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* - Clock source selection.
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* .
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* @ingroup STM8S
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*/
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/**
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* @defgroup STM8S_PAL STM8S PAL Support
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* @details The STM8S PAL driver uses the GPIO peripherals.
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*
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* @section stm8s_pal_1 Supported HW resources
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* - GPIOA.
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* - GPIOB.
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* - GPIOC.
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* - GPIOD.
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* - GPIOE.
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* - GPIOF.
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* - GPIOG (where present).
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* - GPIOH (where present).
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* - GPIOI (where present).
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* .
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* @section stm8s_pal_2 STM8S PAL driver implementation features
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* The PAL driver implementation fully supports the following hardware
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* capabilities:
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* - 8 bits wide ports.
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* - Atomic set/reset/toggle functions because special STM8S instruction set.
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* - Output latched regardless of the pad setting.
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* - Direct read of input pads regardless of the pad setting.
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* .
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* @section stm8s_pal_3 Supported PAL setup modes
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* The STM8S PAL driver supports the following I/O modes:
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* - @p PAL_MODE_RESET.
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* - @p PAL_MODE_UNCONNECTED.
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* - @p PAL_MODE_INPUT.
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* - @p PAL_MODE_INPUT_PULLUP.
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* - @p PAL_MODE_OUTPUT_PUSHPULL.
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* - @p PAL_MODE_OUTPUT_OPENDRAIN.
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* .
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* Any attempt to setup an invalid mode is ignored.
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*
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* @section stm8s_pal_4 Suboptimal behavior
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* The STM8S GPIO is less than optimal in several areas, the limitations
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* should be taken in account while using the PAL driver:
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* - Bus/group writing is not atomic.
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* - Pad/group mode setup is not atomic.
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* .
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* @ingroup STM8S
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*/
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/**
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* @defgroup STM8S_SERIAL STM8S Serial Support
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* @details The STM8S Serial driver uses the UART peripherals in a
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* buffered, interrupt driven, implementation.
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*
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* @section stm8s_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* - UART1.
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* - UART2 (where present).
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* - UART3 (where present).
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* .
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* @section stm8s_serial_2 STM8S Serial driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Fully interrupt driven.
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* .
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* @ingroup STM8S
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*/
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/**
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* @defgroup STM8S_SPI STM8S SPI Support
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* @details The SPI driver supports the STM8S SPI peripheral in an interrupt
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* driven implementation.
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* @note Being the SPI a fast peripheral, much care must be taken to
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* not saturate the CPU bandwidth with an excessive IRQ rate. The
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* maximum transfer bit rate is likely limited by the IRQ
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* handling.
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*
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* @section stm8s_spi_1 Supported HW resources
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* - SPI.
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* .
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* @section stm8s_spi_2 STM8S SPI driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Fully interrupt driven.
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* .
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* @ingroup STM8S
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*/
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