177 lines
9.3 KiB
C
177 lines
9.3 KiB
C
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/************************************************************************
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* (c) Copyright Freescale Semiconductor, Inc 2012, All Rights Reserved *
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*************************************************************************
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*************************************************************************
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* *
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* Standard Software Flash Driver For FTFx *
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* *
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* FILE NAME : SSD_FTFx_Common.h *
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* DATE : Jun 20, 2012 *
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* *
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* AUTHOR : FPT Team *
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* E-mail : b39392@freescale.com *
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* *
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*************************************************************************/
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/************************** CHANGES *************************************
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0.0.1 06.20.2012 FPT Team Initial Version
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*************************************************************************/
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#ifndef _SSD_FTFx_COMMON_H_
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#define _SSD_FTFx_COMMON_H_
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#include "SSD_Types.h"
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/*------------------------- Configuration Macros -----------------------*/
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/* Define derivatives with rule: FTFx_KX_Pblocksize_Dblocksize_EERAMsize_Psectorsize_Dsectorsize */
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#define FTFx_KX_256K_256K_4K_2K_2K 1 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_512K_0K_0K_2K_0K 2 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_JX_128K_32K_2K_1K_1K 3 /* ColdFire core */
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#define FTFx_FX_256K_32K_2K_1K_1K 4 /* ColdFire core */
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#define FTFx_KX_512K_512K_16K_4K_4K 5 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_1024K_0K_16K_4K_0K 6 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_32K_0K_0K_1K_0K 7 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_32K_32K_2K_1K_1K 8 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_64K_0K_0K_1K_0K 9 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_64K_32K_2K_1K_1K 10 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_128K_0K_0K_1K_0K 11 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_128K_32K_2K_1K_1K 12 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_64K_32K_2K_2K_1K 13 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_128K_32K_2K_2K_1K 14 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_KX_256K_32K_2K_2K_1K 15 /* Kinetis - ARM Cortex M4 core */
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#define FTFx_NX_256K_32K_2K_2K_1K 16 /* Nevis2 - 56800EX 32 bit DSC core */
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#define FTFx_NX_128K_32K_2K_2K_1K 17 /* Nevis2 - 56800EX 32 bit DSC core */
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#define FTFx_NX_96K_32K_2K_2K_1K 18 /* Nevis2 - 56800EX 32 bit DSC core */
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#define FTFx_NX_64K_32K_2K_2K_1K 19 /* Nevis2 - 56800EX 32 bit DSC core */
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#define FTFx_LX_128K_0K_0K_1K_0K 20 /* L2K - ARM Cortex M0 core */
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#define FTFx_LX_64K_0K_0K_1K_0K 21 /* L2K - ARM Cortex M0 core */
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#define FTFx_LX_32K_0K_0K_1K_0K 22 /* L2K & L1PT - ARM Cortex M0 core */
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#define FTFx_LX_16K_0K_0K_1K_0K 23 /* L1PT - ARM Cortex M0 core */
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#define FTFx_LX_8K_0K_0K_1K_0K 24 /* L1PT - ARM Cortex M0 core */
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#define FTFx_AX_64K_0K_0K_1K_0K 25 /* Anguilla_Silver - 56800EX 32 bit DSC core */
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#define FTFx_AX_48K_0K_0K_1K_0K 26 /* Anguilla_Silver - 56800EX 32 bit DSC core */
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#define FTFx_AX_32K_0K_0K_1K_0K 27 /* Anguilla_Silver - 56800EX 32 bit DSC core */
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#define FTFx_AX_16K_0K_0K_1K_0K 28 /* Anguilla_Silver - 56800EX 32 bit DSC core */
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/* Define compiler */
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#define CW 0 /* CodeWarrior Compiler */
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#define IAR 1 /* IAR Compiler */
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/* Endianness */
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#define BIG_ENDIAN 0 /* Big Endian */
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#define LITTLE_ENDIAN 1 /* Little Endian */
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/* cpu cores */
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#define COLDFIRE 0 /* ColdFire core */
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#define ARM_CM4 1 /* ARM Cortex M4 core */
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#define DSC_56800EX 2 /* 32 bit DSC core */
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#define ARM_CM0PLUS 3 /* ARM Cortex M0 core */
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/* Word size */
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#define FTFx_WORD_SIZE 0x0002 /* 2 bytes */
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/* Longword size */
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#define FTFx_LONGWORD_SIZE 0x0004 /* 4 bytes */
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/* Phrase size */
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#define FTFx_PHRASE_SIZE 0x0008 /* 8 bytes */
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/* Double-phrase size */
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#define FTFx_DPHRASE_SIZE 0x0010 /* 16 bytes */
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/*------------ Return Code Definition for FTFx SSD ---------------------*/
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#define FTFx_OK 0x0000
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#define FTFx_ERR_SIZE 0x0001
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#define FTFx_ERR_RANGE 0x0002
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#define FTFx_ERR_ACCERR 0x0004
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#define FTFx_ERR_PVIOL 0x0008
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#define FTFx_ERR_MGSTAT0 0x0010
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#define FTFx_ERR_CHANGEPROT 0x0020
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#define FTFx_ERR_EEESIZE 0x0040
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#define FTFx_ERR_EFLASHSIZE 0x0080
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#define FTFx_ERR_ADDR 0x0100
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#define FTFx_ERR_NOEEE 0x0200
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#define FTFx_ERR_EFLASHONLY 0x0400
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#define FTFx_ERR_DFLASHONLY 0x0800
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#define FTFx_ERR_RDCOLERR 0x1000
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#define FTFx_ERR_RAMRDY 0x2000
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/* Flash security status */
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#define FLASH_SECURITY_STATE_KEYEN 0x80
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#define FLASH_SECURITY_STATE_UNSECURED 0x02
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#define FLASH_NOT_SECURE 0x01
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#define FLASH_SECURE_BACKDOOR_ENABLED 0x02
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#define FLASH_SECURE_BACKDOOR_DISABLED 0x04
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/* macro for flash configuration field offset */
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#define FLASH_CNFG_START_ADDRESS 0x400
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#define FLASH_CNFG_END_ADDRESS 0x40F
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/* EERAM Function Control Code */
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#define EEE_ENABLE 0x00
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#define EEE_DISABLE 0xFF
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/*-------------- Read/Write/Set/Clear Operation Macros -----------------*/
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#define REG_BIT_SET(address, mask) (*(VUINT8*)(address) |= (mask))
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#define REG_BIT_CLEAR(address, mask) (*(VUINT8*)(address) &= ~(mask))
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#define REG_BIT_TEST(address, mask) (*(VUINT8 *)(address) & (UINT8)(mask))
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#define REG_WRITE(address, value) (*(VUINT8*)(address) = (value))
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#define REG_READ(address) ((UINT8)(*(VUINT8*)(address)))
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#define REG_WRITE32(address, value) (*(VUINT32*)(address) = (value))
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#define REG_READ32(address) ((UINT32)(*(VUINT32*)(address)))
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#define WRITE8(address, value) (*(VUINT8*)(address) = (value))
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#define READ8(address) ((UINT8)(*(VUINT8*)(address)))
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#define SET8(address, value) (*(VUINT8*)(address) |= (value))
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#define CLEAR8(address, value) (*(VUINT8*)(address) &= ~(value))
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#define TEST8(address, value) (*(VUINT8*)(address) & (value))
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#define WRITE16(address, value) (*(VUINT16*)(address) = (value))
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#define READ16(address) ((UINT16)(*(VUINT16*)(address)))
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#define SET16(address, value) (*(VUINT16*)(address) |= (value))
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#define CLEAR16(address, value) (*(VUINT16*)(address) &= ~(value))
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#define TEST16(address, value) (*(VUINT16*)(address) & (value))
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#define WRITE32(address, value) (*(VUINT32*)(address) = (value))
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#define READ32(address) ((UINT32)(*(VUINT32*)(address)))
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#define SET32(address, value) (*(VUINT32*)(address) |= (value))
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#define CLEAR32(address, value) (*(VUINT32*)(address) &= ~(value))
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#define TEST32(address, value) (*(VUINT32*)(address) & (value))
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/*--------------------- CallBack function period -----------------------*/
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#define FLASH_CALLBACK_CS 1 /* Check Sum */
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/*-------------------- Callback function prototype ---------------------*/
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typedef void (* PCALLBACK)(void);
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typedef BOOL (* PFLASH_SWAP_CALLBACK)(UINT8);
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/*--------------------Null Callback function defination ----------------*/
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#define NULL_CALLBACK ((PCALLBACK)0xFFFFFFFF)
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#define NULL_SWAP_CALLBACK ((PFLASH_SWAP_CALLBACK)0xFFFFFFFF)
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/*---------------- Flash SSD Configuration Structure -------------------*/
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typedef struct _ssd_config
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{
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UINT32 ftfxRegBase; /* FTFx control register base */
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UINT32 PFlashBlockBase; /* base address of PFlash block */
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UINT32 PFlashBlockSize; /* size of PFlash block */
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UINT32 DFlashBlockBase; /* base address of DFlash block */
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UINT32 DFlashBlockSize; /* size of DFlash block */
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UINT32 EERAMBlockBase; /* base address of EERAM block */
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UINT32 EERAMBlockSize; /* size of EERAM block */
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UINT32 EEEBlockSize; /* size of EEE block */
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BOOL DebugEnable; /* background debug mode enable bit */
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PCALLBACK CallBack; /* pointer to callback function */
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} FLASH_SSD_CONFIG, *PFLASH_SSD_CONFIG;
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/* PFlash swap states */
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#define FTFx_SWAP_UNINIT 0x00
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#define FTFx_SWAP_READY 0x01
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#define FTFx_SWAP_INIT 0x01
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#define FTFx_SWAP_UPDATE 0x02
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#define FTFx_SWAP_UPDATE_ERASED 0x03
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#define FTFx_SWAP_COMPLETE 0x04
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#endif /* _SSD_FTFx_COMMON_H_ */
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