545 lines
15 KiB
C
545 lines
15 KiB
C
/******************************************************************************/
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/* Copyright (c) 2016 MD Automotive Controls. Original Work. */
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/* License: http://www.gnu.org/licenses/gpl.html GPL version 2 or higher */
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/******************************************************************************/
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/* CONTEXT:KERNEL */
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/* PACKAGE TITLE: CAN Hardware Abstraction */
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/* DESCRIPTION: This code provides functions for interacting with */
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/* the CAN hardware module/s */
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/* FILE NAME: CANHA.c */
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/* REVISION HISTORY: 28-03-2016 | 1.0 | Initial revision */
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/* */
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/******************************************************************************/
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#include <string.h>
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#include "build.h"
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#include "percan.h"
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#include "macros.h"
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#include "PERCAN.h"
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const CANHA_tstTimingSettings CANHA_astTimingSettings[] = CANHA_nSetTimingData;
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static sint32 CANHA_u32GetCANIndex(IOAPI_tenEHIOResource);
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#define CANHA_nTimingOptionsCount (sizeof(CANHA_astTimingSettings) / sizeof(CANHA_tstTimingSettings))
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void CANHA_vStart(uint32* const u32Stat)
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{
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}
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uint32 CANHA_u32InitBus(IOAPI_tenEHIOResource enEHIOResource, IOAPI_tstPortConfigCB* pstPortConfigCB)
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{
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tstCANModule* pstCAN;
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IRQn_Type nCANIRQ;
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sint32 i32IDX = CANHA_u32GetCANIndex(enEHIOResource);
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uint32 u32MuxSel = ~0ul;
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#if defined(BUILD_MK60) || defined(BUILD_MK64)
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REGSET_tstReg32Val astCANReg32Val[54];
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uint8 u8RegIDX = 0;
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uint8 u8TimingIDX;
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uint8 u8PRESDIV;
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uint8 u8SJW = 3;
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uint8 u8TSEG1 = 15;
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uint8 u8TSEG2 = 7;
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uint8 u8MBXIDX;
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if ((-1 != i32IDX) && (TRUE == DLL_boInitDLLChannel(enEHIOResource, pstPortConfigCB)))
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{
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switch (enEHIOResource)
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{
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case EH_VIO_CAN1:
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{
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pstCAN = (CAN_Type*)CAN0_BASE;
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nCANIRQ = CAN0_ORed_Message_buffer_IRQn;
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/* turn on FLEXCAN1 clock */
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SIM_vSetReg32(SIM_SCGC6, SIM_SCGC6_FLEXCAN0_MASK);
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break;
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}
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#ifdef BUILD_MK60
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case EH_VIO_CAN2:
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{
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pstCAN = (CAN_Type*)CAN1_BASE;
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nCANIRQ = CAN1_ORed_Message_buffer_IRQn;
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/* turn on FLEXCAN2 clock */
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SIM_vSetReg32(SIM_SCGC3, SIM_SCGC3_FLEXCAN1_MASK);
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break;
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}
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#endif
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default:
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{
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pstCAN = NULL;
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break;
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}
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}
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if (NULL != pstCAN)
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{
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for (u8TimingIDX = 0; u8TimingIDX < CANHA_nTimingOptionsCount; u8TimingIDX++)
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{
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if (CANHA_astTimingSettings[u8TimingIDX].u32BitRate == pstPortConfigCB->u32BaudRateHz)
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{
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u8PRESDIV = CANHA_astTimingSettings[u8TimingIDX].u8PRESDIV;
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u8SJW = CANHA_astTimingSettings[u8TimingIDX].u8SJW;
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u8TSEG1 = CANHA_astTimingSettings[u8TimingIDX].u8TSEG1;
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u8TSEG2 = CANHA_astTimingSettings[u8TimingIDX].u8TSEG2;
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break;
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}
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}
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pstCAN -> MCR &= ~CAN_MCR_MDIS_MASK;
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pstCAN -> MCR |= CAN_MCR_SOFTRST_MASK;
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while(pstCAN -> MCR & CAN_MCR_SOFTRST_MASK);
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pstCAN -> MCR |= CAN_MCR_FRZ_MASK;
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pstCAN -> MCR |= CAN_MCR_HALT_MASK;
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pstCAN -> MCR |= CAN_MCR_IRMQ_MASK;
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while(!(pstCAN -> MCR & CAN_MCR_FRZACK_MASK));
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, CTRL1));
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astCANReg32Val[u8RegIDX].val = CAN_CTRL1_PRESDIV(u8PRESDIV)
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+ CAN_CTRL1_PSEG1(u8TSEG1)
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+ CAN_CTRL1_PSEG2(u8TSEG2)
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+ CAN_CTRL1_RJW(u8SJW);
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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/* Set the MBX RX CS fields */
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for (u8MBXIDX = 0; u8MBXIDX < CAN_nCANRXMailboxCount; u8MBXIDX++)
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{
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, MB[u8MBXIDX].CS));
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astCANReg32Val[u8RegIDX].val = CAN_CS_CODE(CAN_nCANMBXEmpty);
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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}
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/* Set the MBX TX CS fields */
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for (u8MBXIDX = CAN_nCANRXMailboxCount; u8MBXIDX < CAN_nCANMailboxCount; u8MBXIDX++)
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{
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, MB[u8MBXIDX].CS));
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astCANReg32Val[u8RegIDX].val = CAN_CS_CODE(CAN_nCANMBXInactive2);
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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}
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/* Set the global diag and diag MB ID fields */
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, MB[0].ID));
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astCANReg32Val[u8RegIDX].val = CAN_ID_STD(pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32GlobalCANDiagAddress)
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| CAN_ID_PRIO(0);
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, MB[1].ID));
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astCANReg32Val[u8RegIDX].val = CAN_ID_STD(pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANDiagAddress)
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| CAN_ID_PRIO(0);
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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/* Set the global diag and diag ID mask fields */
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, RXIMR[0]));
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astCANReg32Val[u8RegIDX].val = 0x7ff << CAN_ID_STD_SHIFT;
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, RXIMR[1]));
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astCANReg32Val[u8RegIDX].val = 0x7ff << CAN_ID_STD_SHIFT;
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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/* Set the priority MB ID fields */
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for (u8MBXIDX = 2; u8MBXIDX < 6; u8MBXIDX++)
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{
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, MB[u8MBXIDX].ID));
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if (0x800u > pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[u8MBXIDX - 2])
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{
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astCANReg32Val[u8RegIDX].val = CAN_ID_STD(pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[u8MBXIDX - 2])
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| CAN_ID_PRIO(0);
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}
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else
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{
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astCANReg32Val[u8RegIDX].val = CAN_ID_EXT(pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[u8MBXIDX - 2])
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| CAN_ID_PRIO(0);
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}
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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}
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/* Set the priority ID mask fields */
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for (u8MBXIDX = 2; u8MBXIDX < 6; u8MBXIDX++)
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{
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, RXIMR[u8MBXIDX]));
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if (0x800u > pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[u8MBXIDX - 2])
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{
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astCANReg32Val[u8RegIDX].val = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityMask[u8MBXIDX - 2] << CAN_ID_STD_SHIFT;
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}
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else
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{
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astCANReg32Val[u8RegIDX].val = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityMask[u8MBXIDX - 2] << CAN_ID_EXT_SHIFT;
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}
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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}
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/* Clear remaining MB ID fields */
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for (u8MBXIDX = 6; u8MBXIDX < 16; u8MBXIDX++)
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{
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, MB[u8MBXIDX].ID));
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astCANReg32Val[u8RegIDX].val = 0u;
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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}
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/* Clear the remaining ID mask fields */
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for (u8MBXIDX = 6; u8MBXIDX < 16; u8MBXIDX++)
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{
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astCANReg32Val[u8RegIDX].reg = (volatile uint32*)((uint32)pstCAN + (uint32)offsetof(CAN_Type, RXIMR[u8MBXIDX]));
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astCANReg32Val[u8RegIDX].val = 0u;
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astCANReg32Val[u8RegIDX++].writeMode = REGSET_enOverwrite;
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}
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astCANReg32Val[u8RegIDX].reg = NULL;
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REGSET_vInitReg32(&astCANReg32Val[0]);
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pstCAN -> MCR &= ~CAN_MCR_HALT_MASK;
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while((pstCAN -> MCR) & CAN_MCR_FRZACK_MASK);
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IRQ_vEnableIRQ(nCANIRQ, IRQ_enPRIO_15, CAN_vInterrupt, NULL);
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pstCAN -> IMASK1 = 0x00000FFF;
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u32MuxSel = 2;
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}
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}
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#endif
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#ifdef BUILD_SAM3X8E
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can_mb_conf_t stMBConfig;
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if ((-1 != i32IDX) && (TRUE == DLL_boInitDLLChannel(enEHIOResource, pstPortConfigCB)))
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{
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switch (enEHIOResource)
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{
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case EH_VIO_CAN1:
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{
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pstCAN = (tstCANModule*)CAN0;
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nCANIRQ = CAN0_IRQn;
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break;
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}
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case EH_VIO_CAN2:
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{
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pstCAN = (tstCANModule*)CAN1;
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nCANIRQ = CAN1_IRQn;
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break;
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}
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default:
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{
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pstCAN = NULL;
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break;
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}
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}
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if (NULL != pstCAN)
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{
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/* turn on peripheral clock */
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SIM_boEnablePeripheralClock(nCANIRQ);
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can_init(pstCAN, SYS_FREQ_BUS, pstPortConfigCB->u32BaudRateHz / 1000u);
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stMBConfig.ul_mb_idx = 0;
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stMBConfig.uc_obj_type = CAN_MB_TYPE_RX;
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stMBConfig.uc_id_ver = pstPortConfigCB->enLLProtocol == PROTAPI_enLLCAN11 ? 0 : 1;
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stMBConfig.uc_length = 8;
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stMBConfig.uc_tx_prio = 0;
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stMBConfig.ul_status = 0;
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if (pstPortConfigCB->enLLProtocol == PROTAPI_enLLCAN11)
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{
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stMBConfig.ul_id_msk = 0x7ff;
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}
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else
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{
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stMBConfig.ul_id_msk = 0x7ffffff;
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}
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stMBConfig.ul_id = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANDiagAddress;
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stMBConfig.ul_fid = 0;
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stMBConfig.ul_datal = 0;
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stMBConfig.ul_datah = 0;
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//1
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stMBConfig.ul_id = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32GlobalCANDiagAddress;
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//2
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stMBConfig.ul_id_msk = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityMask[0];
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stMBConfig.ul_id = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[0];
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//3
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stMBConfig.ul_id_msk = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityMask[1];
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stMBConfig.ul_id = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[1];
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//4
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stMBConfig.ul_id_msk = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityMask[2];
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stMBConfig.ul_id = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[2];
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//5
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stMBConfig.ul_id_msk = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityMask[3];
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stMBConfig.ul_id = pstPortConfigCB->stNetConfig.uNetInfo.stCANNetInfo.u32CANPriorityAddress[3];
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//6
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stMBConfig.uc_obj_type = CAN_MB_TYPE_TX;
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stMBConfig.ul_id_msk = 0;
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stMBConfig.ul_id = 0;
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can_mailbox_init(pstCAN, &stMBConfig);
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stMBConfig.ul_mb_idx++;//7
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can_mailbox_init(pstCAN, &stMBConfig);
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can_enable_interrupt(pstCAN, 0x3f);
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IRQ_vEnableIRQ(nCANIRQ, IRQ_enPRIO_15, CAN_vInterrupt, NULL);
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u32MuxSel = 0;
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}
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}
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#endif //BUILD SAM3X8E
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return u32MuxSel;
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}
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void CANHA_vRun(uint32* const u32Stat)
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{
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}
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void CANHA_vInterrupt(IOAPI_tenEHIOResource enEHIOResource)
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{
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CANHA_tstCANMB stCANMB;
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tstCANModule* pstCAN;
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uint32 u32MailboxReadCount = CAN_nCANRXMailboxCount;
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switch (enEHIOResource)
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{
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case EH_VIO_CAN1:
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{
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pstCAN = CAN0;
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break;
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}
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#ifdef BUILD_MK60
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case EH_VIO_CAN2:
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{
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pstCAN = CAN1;
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break;
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}
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#endif //BUILD_MK64
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default:
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{
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pstCAN = NULL;
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}
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}
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if (NULL != pstCAN)
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{
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bool boReadOK = TRUE;
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while ((TRUE == boReadOK) && (0 < u32MailboxReadCount))
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{
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boReadOK = CANHA_boReadMB(pstCAN, &stCANMB);
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if (TRUE == boReadOK)
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{
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DLL_vFrameRXCB(enEHIOResource, (puint8)&stCANMB);
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}
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u32MailboxReadCount--;
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}
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}
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}
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void CANHA_vInitTransfer(IOAPI_tstTransferCB* pstTransferCB)
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{
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tstCANModule* pstCAN = NULL;
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PROTAPI_tstCANMsg* pstCANMsg;
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#if defined(BUILD_MK60) || defined(BUILD_MK64)
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CANHA_tstCANMB* pstCANMB;
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uint32 u32MBXIDX;
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switch (pstTransferCB->enEHIOResource)
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{
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case EH_VIO_CAN1:
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{
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pstCAN = (CAN_Type*)CAN0_BASE;
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break;
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}
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#ifdef BUILD_MK60
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case EH_VIO_CAN2:
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{
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pstCAN = (CAN_Type*)CAN1_BASE;
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break;
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}
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#endif //BUILD_MK60
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default:
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{
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break;
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}
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}
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if (NULL != pstCAN)
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{
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for (u32MBXIDX = CAN_nCANRXMailboxCount; u32MBXIDX < CAN_nCANMailboxCount; u32MBXIDX++)
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{
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if (CAN_nCANMBXInactive2 == ((pstCAN->MB[u32MBXIDX].CS & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT))
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{
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pstCANMB = (CANHA_tstCANMB*)&pstCAN->MB[u32MBXIDX];
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/* Data must be CAN frame so cast the pointer */
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pstCANMsg = (PROTAPI_tstCANMsg*)pstTransferCB->pvData;
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if (0x800u > pstCANMsg->u32ID)
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{
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pstCANMB->u32ID = CAN_ID_STD(pstCANMsg->u32ID)
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| CAN_ID_PRIO(0);
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}
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else
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{
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pstCANMB->u32ID = CAN_ID_EXT(pstCANMsg->u32ID)
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| CAN_ID_PRIO(0);
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}
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pstCANMB->u32DWH = pstCANMsg->u32DWH;
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pstCANMB->u32DWL = pstCANMsg->u32DWL;
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pstCANMB->u32CS = CAN_CS_CODE(CAN_nCANMBXData) |
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CAN_CS_DLC(pstCANMsg->u8DLC);
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break;
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}
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}
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}
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#endif
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#ifdef BUILD_SAM3X8E
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uint32 u32MBIDX;
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switch (pstTransferCB->enEHIOResource)
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{
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case EH_VIO_CAN1:
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{
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pstCAN = CAN0;
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break;
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}
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case EH_VIO_CAN2:
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{
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pstCAN = CAN1;
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break;
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}
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default:
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{
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pstCAN = NULL;
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break;
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}
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}
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|
if (NULL != pstCAN)
|
|
{
|
|
/* Data must be CAN frame so cast the pointer */
|
|
pstCANMsg = (PROTAPI_tstCANMsg*)pstTransferCB->pvData;
|
|
(void)CANHA_boWriteMB(pstCAN, pstCANMsg);
|
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}
|
|
#endif
|
|
|
|
|
|
}
|
|
|
|
bool CANHA_boReadMB(tstCANModule* pstCAN, CANHA_tstCANMB* pstCANMB)
|
|
{
|
|
bool boReadOK = false;
|
|
uint8 u8MBXIDX;
|
|
uint32 u32MBXMask;
|
|
|
|
#ifdef BUILD_SAM3X8E
|
|
can_mb_conf_t mailbox;
|
|
|
|
uint8 u32MBMask = 1;
|
|
uint32 u32TempSource;
|
|
uint32 u32TempDest;
|
|
|
|
|
|
while (u8MBIDX < 8)
|
|
{
|
|
if (0 < (u32MBMask & (pstCAN->CAN_SR)))
|
|
{
|
|
break;
|
|
}
|
|
u32MBMask *= 2;
|
|
u8MBIDX++;
|
|
}
|
|
|
|
if (u8MBIDX < 8)
|
|
{
|
|
mailbox.ul_mb_idx = u8MBIDX;
|
|
mailbox.ul_status = pstCAN->CAN_MB[u8MBIDX].CAN_MSR;
|
|
|
|
can_mailbox_read(pstCAN, &mailbox);
|
|
|
|
pstCANMB->u32ID = mailbox.ul_fid;
|
|
|
|
u32TempSource = mailbox.ul_datal;
|
|
u32TempDest = HTONL(u32TempSource);
|
|
pstCANMB->u32DWH = u32TempDest;
|
|
|
|
u32TempSource = mailbox.ul_datah;
|
|
u32TempDest = HTONL(u32TempSource);
|
|
pstCANMB->u32DWL = u32TempDest;
|
|
|
|
boReadOK = true;
|
|
}
|
|
#endif //BUILD_SAM3X8E
|
|
|
|
#ifdef BUILD_MK64
|
|
u32MBXMask = 1;
|
|
|
|
for (u8MBXIDX = 0; u8MBXIDX < CAN_nCANRXMailboxCount; u8MBXIDX++)
|
|
{
|
|
if (CAN_nCANMBXFull == ((pstCAN->MB[u8MBXIDX].CS & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT) &&
|
|
(0 != (u32MBXMask & pstCAN->IFLAG1)))
|
|
{
|
|
boReadOK = true;
|
|
pstCANMB->u32CS = pstCAN->MB[u8MBXIDX].CS;
|
|
pstCANMB->u32ID = pstCAN->MB[u8MBXIDX].ID;
|
|
pstCANMB->u32DWH = pstCAN->MB[u8MBXIDX].WORD0;
|
|
pstCANMB->u32DWL = pstCAN->MB[u8MBXIDX].WORD1;
|
|
pstCAN->IFLAG1 = u32MBXMask;
|
|
break;
|
|
}
|
|
|
|
u32MBXMask *= 2;
|
|
}
|
|
#endif //BUILD_SAM3X8E
|
|
|
|
return boReadOK;
|
|
}
|
|
|
|
|
|
void CANHA_vTerminate(uint32* const u32Stat)
|
|
{
|
|
|
|
}
|
|
|
|
static sint32 CANHA_u32GetCANIndex(IOAPI_tenEHIOResource enEHIOResource)
|
|
{
|
|
sint32 i32IDX = -1;
|
|
#ifdef BUILD_MK60
|
|
if ((EH_VIO_CAN1 <= enEHIOResource) && (EH_VIO_CAN2 >= enEHIOResource))
|
|
#endif //BUILD_MK60
|
|
|
|
#ifdef BUILD_MK64
|
|
if (EH_VIO_CAN1 <= enEHIOResource)
|
|
#endif //BUILD_MK64
|
|
{
|
|
i32IDX = enEHIOResource - EH_VIO_CAN1;
|
|
}
|
|
|
|
return i32IDX;
|
|
}
|
|
|
|
|
|
|
|
|