This commit is contained in:
rusefi 2023-06-03 21:06:07 -04:00
parent 4fb65fd60f
commit 8c8e116494
3 changed files with 58 additions and 22 deletions

View File

@ -3,10 +3,12 @@
"active_layer": 0, "active_layer": 0,
"active_layer_preset": "", "active_layer_preset": "",
"auto_track_width": true, "auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [], "hidden_nets": [],
"high_contrast_mode": 0, "high_contrast_mode": 0,
"net_color_mode": 1, "net_color_mode": 1,
"opacity": { "opacity": {
"images": 0.6,
"pads": 0.7799999713897705, "pads": 0.7799999713897705,
"tracks": 1.0, "tracks": 1.0,
"vias": 0.7900000214576721, "vias": 0.7900000214576721,

View File

@ -1,5 +1,6 @@
{ {
"board": { "board": {
"3dviewports": [],
"design_settings": { "design_settings": {
"defaults": { "defaults": {
"board_outline_line_width": 0.19999999999999998, "board_outline_line_width": 0.19999999999999998,
@ -181,7 +182,8 @@
"zones_allow_external_fillets": false, "zones_allow_external_fillets": false,
"zones_use_no_outline": true "zones_use_no_outline": true
}, },
"layer_presets": [] "layer_presets": [],
"viewports": []
}, },
"boards": [], "boards": [],
"cvpcb": { "cvpcb": {
@ -365,18 +367,23 @@
"rule_severities": { "rule_severities": {
"bus_definition_conflict": "error", "bus_definition_conflict": "error",
"bus_entry_needed": "error", "bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error", "bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error", "bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error", "different_unit_footprint": "error",
"different_unit_net": "error", "different_unit_net": "error",
"duplicate_reference": "error", "duplicate_reference": "error",
"duplicate_sheet_names": "error", "duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error", "extra_units": "error",
"global_label_dangling": "warning", "global_label_dangling": "warning",
"hier_label_mismatch": "error", "hier_label_mismatch": "error",
"label_dangling": "error", "label_dangling": "error",
"lib_symbol_issues": "warning", "lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning", "multiple_net_names": "warning",
"net_not_bus_member": "ignore", "net_not_bus_member": "ignore",
"no_connect_connected": "warning", "no_connect_connected": "warning",
@ -386,6 +393,7 @@
"pin_to_pin": "warning", "pin_to_pin": "warning",
"power_pin_not_driven": "ignore", "power_pin_not_driven": "ignore",
"similar_labels": "warning", "similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error", "unannotated": "error",
"unit_value_mismatch": "error", "unit_value_mismatch": "error",
"unresolved_variable": "error", "unresolved_variable": "error",
@ -403,7 +411,7 @@
"net_settings": { "net_settings": {
"classes": [ "classes": [
{ {
"bus_width": 12.0, "bus_width": 12,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.2, "diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
@ -417,10 +425,10 @@
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6.0 "wire_width": 6
}, },
{ {
"bus_width": 12.0, "bus_width": 12,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.254, "diff_pair_gap": 0.254,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
@ -429,18 +437,15 @@
"microvia_diameter": 0.508, "microvia_diameter": 0.508,
"microvia_drill": 0.127, "microvia_drill": 0.127,
"name": "GND", "name": "GND",
"nets": [
"GND"
],
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6.0 "wire_width": 6
}, },
{ {
"bus_width": 12.0, "bus_width": 12,
"clearance": 0.4, "clearance": 0.4,
"diff_pair_gap": 0.2, "diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
@ -449,26 +454,49 @@
"microvia_diameter": 0.508, "microvia_diameter": 0.508,
"microvia_drill": 0.127, "microvia_drill": 0.127,
"name": "IN_CRANK", "name": "IN_CRANK",
"nets": [
"/A8",
"/A9",
"/IN_CAM_VR+",
"/IN_CAM_VR-",
"/IN_CRANK+",
"/IN_CRANK-"
],
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6.0 "wire_width": 6
} }
], ],
"meta": { "meta": {
"version": 2 "version": 3
}, },
"net_colors": null "net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "GND",
"pattern": "GND"
},
{
"netclass": "IN_CRANK",
"pattern": "/A8"
},
{
"netclass": "IN_CRANK",
"pattern": "/A9"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CAM_VR+"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CAM_VR-"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CRANK+"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CRANK-"
}
]
}, },
"pcbnew": { "pcbnew": {
"last_paths": { "last_paths": {
@ -484,6 +512,8 @@
"schematic": { "schematic": {
"annotate_start_num": 1000, "annotate_start_num": 1000,
"drawing": { "drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0, "default_bus_thickness": 12.0,
"default_junction_size": 40.0, "default_junction_size": 40.0,
"default_line_thickness": 6.0, "default_line_thickness": 6.0,
@ -518,7 +548,11 @@
"page_layout_descr_file": "kicad6-libraries/Border.kicad_wks", "page_layout_descr_file": "kicad6-libraries/Border.kicad_wks",
"plot_directory": "gerber/", "plot_directory": "gerber/",
"spice_adjust_passive_values": false, "spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65, "subpart_first_id": 65,
"subpart_id_separator": 0 "subpart_id_separator": 0
}, },

@ -1 +1 @@
Subproject commit db562ba9c1676e8cd117dd0bab22ead44a21c2a2 Subproject commit c9ba42002ae083f678554f688317d031e38309e6