This commit is contained in:
Vladimir Vinogradov 2023-06-20 00:13:52 +03:00
parent bba4732fa9
commit 9d38f51e7a
5 changed files with 12833 additions and 8825 deletions

@ -1 +1 @@
Subproject commit 4b2987f141be103e6708a54ecadcec790d51ef8f
Subproject commit 568b68e12a2df30d583b81b581547f96c92e5f95

File diff suppressed because it is too large Load Diff

View File

@ -86,20 +86,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "ignore",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -109,9 +115,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "error",
@ -120,7 +131,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "ignore",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
@ -130,18 +140,63 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.15,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.09999999999999999,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.127,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.29999,
"min_track_width": 0.15,
"min_via_annular_width": 0.15,
"min_via_diameter": 0.3,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.2,
@ -411,7 +466,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25,
@ -425,10 +480,10 @@
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.254,
"diff_pair_via_gap": 0.25,
@ -437,16 +492,15 @@
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "GND",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.4,
"diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25,
@ -455,50 +509,20 @@
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "IN_CRANK",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "GND",
"pattern": "GND"
},
{
"netclass": "IN_CRANK",
"pattern": "/A8"
},
{
"netclass": "IN_CRANK",
"pattern": "/A9"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CAM_VR+"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CAM_VR-"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CRANK+"
},
{
"netclass": "IN_CRANK",
"pattern": "/IN_CRANK-"
}
]
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

@ -1 +1 @@
Subproject commit a31162bae51eef4db6cbb0029feda82056933ad8
Subproject commit 03bf83bc41a94493b883625a0875a41faefd3c53

@ -1 +1 @@
Subproject commit c9ba42002ae083f678554f688317d031e38309e6
Subproject commit a94ebd3fa1f0d04625b9a04affa1ee210521cff5