/**
  ******************************************************************************
  * @file    system_stm32f7xx.c
  * @author  MCD Application Team
  * @version V1.0.0
  * @date    22-April-2016
  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
  *
  *   This file provides two functions and one global variable to be called from
  *   user application:
  *      - SystemInit(): This function is called at startup just after reset and
  *                      before branch to main program. This call is made inside
  *                      the "startup_stm32f7xx.s" file.
  *
  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  *                                  by the user application to setup the SysTick
  *                                  timer or configure other parameters.
  *
  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  *                                 be called whenever the core clock is changed
  *                                 during program execution.
  *
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/** @addtogroup CMSIS
  * @{
  */

/** @addtogroup stm32f7xx_system
  * @{
  */

/** @addtogroup STM32F7xx_System_Private_Includes
  * @{
  */

#include "stm32f7xx.h"
#include "drivers/system.h"
#include "system_stm32f7xx.h"
#include "platform.h"
#include "drivers/persistent.h"

#if !defined  (HSE_VALUE)
  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */

#if !defined  (HSI_VALUE)
  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */

#define PLL_M     8
#define PLL_N     432
#define PLL_P     RCC_PLLP_DIV2 /* 2 */
#define PLL_Q     9

#define PLL_SAIN  384
#define PLL_SAIQ  7
#define PLL_SAIP  RCC_PLLSAIP_DIV8

/**
  * @}
  */

/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
  * @{
  */

/**
  * @}
  */

/** @addtogroup STM32F7xx_System_Private_Defines
  * @{
  */

/**
  * @}
  */

/** @addtogroup STM32F7xx_System_Private_Macros
  * @{
  */

/**
  * @}
  */

/** @addtogroup STM32F7xx_System_Private_Variables
  * @{
  */

  /* This variable is updated in three ways:
      1) by calling CMSIS function SystemCoreClockUpdate()
      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
         Note: If you use this function to configure the system clock; then there
               is no need to call the 2 first functions listed above, since SystemCoreClock
               variable is updated automatically.
  */
  uint32_t SystemCoreClock;
  uint32_t pll_p = PLL_P, pll_n = PLL_N, pll_q = PLL_Q;

  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};

/**
  * @}
  */

/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
  * @{
  */

  /// TODO: F7 check if this is the best configuration for the clocks.
  // current settings are just a copy from one of the example projects
  void SystemClock_Config(void)
  {
      RCC_ClkInitTypeDef RCC_ClkInitStruct;
      RCC_OscInitTypeDef RCC_OscInitStruct;
      RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
      HAL_StatusTypeDef ret;

      __HAL_RCC_PWR_CLK_ENABLE();

      __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

#ifdef CLOCK_SOURCE_USE_HSI
      /* Enable HSI Oscillator and activate PLL with HSI as source */
      RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI;
      RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
      RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
      RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
      RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI;
      RCC_OscInitStruct.PLL.PLLM             = 16;
      RCC_OscInitStruct.PLL.PLLN             = 432;
      RCC_OscInitStruct.PLL.PLLP             = RCC_PLLP_DIV2;
      RCC_OscInitStruct.PLL.PLLQ             = 9;
#else
      /* Enable HSE Oscillator and activate PLL with HSE as source */
      RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
      RCC_OscInitStruct.HSEState = RCC_HSE_ON;
      RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
      RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
      RCC_OscInitStruct.PLL.PLLM = PLL_M;
      RCC_OscInitStruct.PLL.PLLN = pll_n;
      RCC_OscInitStruct.PLL.PLLP = pll_p;
      RCC_OscInitStruct.PLL.PLLQ = pll_q;
#endif

      ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
      if (ret != HAL_OK) {
        while (1);
      }

      /* Activate the OverDrive to reach the 216 MHz Frequency */
      ret = HAL_PWREx_EnableOverDrive();
      if (ret != HAL_OK) {
        while (1);
      }
      /* Select PLLSAI output as USB clock source */
      PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
      PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
      PeriphClkInitStruct.PLLSAI.PLLSAIN = PLL_SAIN;
      PeriphClkInitStruct.PLLSAI.PLLSAIQ = PLL_SAIQ;
      PeriphClkInitStruct.PLLSAI.PLLSAIP = PLL_SAIP;
      if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
        while (1);
      }

      /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
      RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
      RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
      RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
      RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;

      ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
      if (ret != HAL_OK) {
        while (1);
      }

      PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
                                  |RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_USART6
                                  |RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_UART5
                                  |RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_UART8
                                  |RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C3
                                  |RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_I2C4;
      PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
      PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
      PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
      PeriphClkInitStruct.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
      PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1;
      PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
      PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1;
      PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1;
      PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
      PeriphClkInitStruct.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
      PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
      PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1;
      ret = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
      if (ret != HAL_OK) {
          while (1);
      }

      // Configure PLLI2S for 27MHz operation
      // Actual output will be done by mcoInit in drivers/mco.c

      PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_PLLI2S;
      PeriphClkInitStruct.PLLI2S.PLLI2SN = 216;
      PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
      PeriphClkInitStruct.PLLI2S.PLLI2SQ = 2;
      PeriphClkInitStruct.PLLI2SDivQ = 1;
      if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
      {
          while (1);
      }

    // Activating the timerprescalers while the APBx prescalers are 1/2/4 will connect the TIMxCLK to HCLK which has been configured to 216MHz
    __HAL_RCC_TIMCLKPRESCALER(RCC_TIMPRES_ACTIVATED);

    SystemCoreClockUpdate();
  }

typedef struct pllConfig_s {
  uint16_t n;
  uint16_t p;
  uint16_t q;
} pllConfig_t;

static const pllConfig_t overclockLevels[] = {
  { PLL_N, PLL_P, PLL_Q },    // default
  { 480, RCC_PLLP_DIV2, 10 }, // 240 MHz
};

void SystemInitOC(void) {
    uint32_t currentOverclockLevel = persistentObjectRead(PERSISTENT_OBJECT_OVERCLOCK_LEVEL);

    if (currentOverclockLevel >= ARRAYLEN(overclockLevels)) {
      return;
    }

    /* PLL setting for overclocking */
    const pllConfig_t * const pll = overclockLevels + currentOverclockLevel;

    pll_n = pll->n;
    pll_p = pll->p;
    pll_q = pll->q;
}

void OverclockRebootIfNecessary(uint32_t overclockLevel)
{
    if (overclockLevel >= ARRAYLEN(overclockLevels)) {
        return;
    }

    const pllConfig_t * const pll = overclockLevels + overclockLevel;

    // Reboot to adjust overclock frequency
    if (SystemCoreClock != (pll->n / pll->p) * 1000000U) {
        persistentObjectWrite(PERSISTENT_OBJECT_OVERCLOCK_LEVEL, overclockLevel);
        __disable_irq();
        NVIC_SystemReset();
    }
}

/**
  * @}
  */

/** @addtogroup STM32F7xx_System_Private_Functions
  * @{
  */

/**
  * @brief  Setup the microcontroller system
  *         Initialize the Embedded Flash Interface, the PLL and update the
  *         SystemFrequency variable.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
    initialiseMemorySections();

    SystemInitOC();

    SystemCoreClock = (pll_n / pll_p) * 1000000;

    /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
#endif
    /* Reset the RCC clock configuration to the default reset state ------------*/
    /* Set HSION bit */
    RCC->CR |= (uint32_t)0x00000001;

    /* Reset CFGR register */
    RCC->CFGR = 0x00000000;

    /* Reset HSEON, CSSON and PLLON bits */
    RCC->CR &= (uint32_t)0xFEF6FFFF;

    /* Reset PLLCFGR register */
    RCC->PLLCFGR = 0x24003010;

    /* Reset HSEBYP bit */
    RCC->CR &= (uint32_t)0xFFFBFFFF;

    /* Disable all interrupts */
    RCC->CIR = 0x00000000;

    /* Configure the Vector Table location add offset address ------------------*/
    extern uint8_t isr_vector_table_base;
    const uint32_t vtorOffset = (uint32_t) &isr_vector_table_base;
#define VTOR_OFFSET_ALIGNMENT 0x200
    if (vtorOffset % VTOR_OFFSET_ALIGNMENT != 0) {
        // ISR vector table base is not 512 byte aligned
        while (1);
    }
    SCB->VTOR = vtorOffset;

    /* Configure the system clock to specified frequency */
    SystemClock_Config();

    if (SystemCoreClock != (pll_n / pll_p) * 1000000) {
        // There is a mismatch between the configured clock and the expected clock in portable.h
        while (1);
    }
}

/**
   * @brief  Update SystemCoreClock variable according to Clock Register Values.
  *         The SystemCoreClock variable contains the core clock (HCLK), it can
  *         be used by the user application to setup the SysTick timer or configure
  *         other parameters.
  *
  * @note   Each time the core clock (HCLK) changes, this function must be called
  *         to update SystemCoreClock variable value. Otherwise, any configuration
  *         based on this variable will be incorrect.
  *
  * @note   - The system frequency computed by this function is not the real
  *           frequency in the chip. It is calculated based on the predefined
  *           constant and the selected clock source:
  *
  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  *
  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  *
  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
  *
  *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
  *             16 MHz) but the real value may vary depending on the variations
  *             in voltage and temperature.
  *
  *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
  *              frequency of the crystal used. Otherwise, this function may
  *              have wrong result.
  *
  *         - The result of this function could be not correct when using fractional
  *           value for HSE crystal.
  *
  * @param  None
  * @retval None
  */
void SystemCoreClockUpdate(void)
{
    uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;

    /* Get SYSCLK source -------------------------------------------------------*/
    tmp = RCC->CFGR & RCC_CFGR_SWS;

    switch (tmp) {
    case 0x00:  /* HSI used as system clock source */
        SystemCoreClock = HSI_VALUE;
        break;
    case 0x04:  /* HSE used as system clock source */
        SystemCoreClock = HSE_VALUE;
        break;
    case 0x08:  /* PLL used as system clock source */

        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
         SYSCLK = PLL_VCO / PLL_P
         */
        pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
        pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;

        if (pllsource != 0) {
            /* HSE used as PLL clock source */
            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
        } else {
            /* HSI used as PLL clock source */
            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
        }

        pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
        SystemCoreClock = pllvco/pllp;
        break;
    default:
        SystemCoreClock = HSI_VALUE;
        break;
    }
    /* Compute HCLK frequency --------------------------------------------------*/
    /* Get HCLK prescaler */
    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
    /* HCLK frequency */
    SystemCoreClock >>= tmp;
}

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
