diff --git a/Makefile b/Makefile
index 58a284d0c..7156073f0 100644
--- a/Makefile
+++ b/Makefile
@@ -46,7 +46,7 @@ FORKNAME = betaflight
CC3D_TARGETS = CC3D CC3D_OPBL
-VALID_TARGETS = NAZE NAZE32PRO OLIMEXINO STM32F3DISCOVERY CHEBUZZF3 $(CC3D_TARGETS) CJMCU EUSTM32F103RC SPRACINGF3 PORT103R SPARKY ALIENFLIGHTF1 ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB RMDO IRCFUSIONF3 AFROMINI SPRACINGF3MINI SPRACINGF3EVO DOGE
+VALID_TARGETS = NAZE NAZE32PRO OLIMEXINO STM32F3DISCOVERY CHEBUZZF3 $(CC3D_TARGETS) CJMCU EUSTM32F103RC SPRACINGF3 PORT103R SPARKY ALIENFLIGHTF1 ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB RMDO IRCFUSIONF3 AFROMINI SPRACINGF3MINI SPRACINGF3EVO DOGE SINGULARITY
# Valid targets for OP VCP support
VCP_VALID_TARGETS = $(CC3D_TARGETS)
@@ -56,9 +56,9 @@ OPBL_VALID_TARGETS = CC3D_OPBL
64K_TARGETS = CJMCU
128K_TARGETS = ALIENFLIGHTF1 $(CC3D_TARGETS) NAZE OLIMEXINO RMDO AFROMINI
-256K_TARGETS = EUSTM32F103RC PORT103R STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB SPRACINGF3MINI SPRACINGF3EVO DOGE
+256K_TARGETS = EUSTM32F103RC PORT103R STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB SPRACINGF3MINI SPRACINGF3EVO DOGE SINGULARITY
-F3_TARGETS = STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB RMDO SPRACINGF3MINI SPRACINGF3EVO DOGE
+F3_TARGETS = STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB RMDO SPRACINGF3MINI SPRACINGF3EVO DOGE SINGULARITY
# note that there is no hardfault debugging startup file assembly handler for other platforms
ifeq ($(DEBUG_HARDFAULTS),F3)
@@ -794,6 +794,20 @@ SPRACINGF3MINI_SRC = \
$(VCP_SRC)
# $(FATFS_SRC)
+SINGULARITY_SRC = \
+ $(STM32F30x_COMMON_SRC) \
+ drivers/accgyro_mpu.c \
+ drivers/accgyro_mpu6050.c \
+ drivers/flash_m25p16.c \
+ drivers/light_ws2811strip.c \
+ drivers/light_ws2811strip_stm32f30x.c \
+ drivers/serial_softserial.c \
+ drivers/serial_usb_vcp.c \
+ io/flashfs.c \
+ $(HIGHEND_SRC) \
+ $(COMMON_SRC) \
+ $(VCP_SRC)
+
# Search path and source files for the ST stdperiph library
VPATH := $(VPATH):$(STDPERIPH_DIR)/src
diff --git a/src/main/config/config.c b/src/main/config/config.c
index 7a5d3d153..081cf9e8d 100755
--- a/src/main/config/config.c
+++ b/src/main/config/config.c
@@ -384,7 +384,7 @@ static void resetConf(void)
masterConfig.version = EEPROM_CONF_VERSION;
masterConfig.mixerMode = MIXER_QUADX;
featureClearAll();
-#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) || defined(MOTOLAB) || defined(SPRACINGF3MINI) || defined(LUX_RACE) || defined(DOGE)
+#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) || defined(MOTOLAB) || defined(SPRACINGF3MINI) || defined(LUX_RACE) || defined(DOGE) || defined(SINGULARITY)
featureSet(FEATURE_RX_PPM);
#endif
@@ -692,6 +692,19 @@ static void resetConf(void)
masterConfig.customMotorMixer[7].yaw = -1.0f;
#endif
+ // alternative defaults settings for SINGULARITY target
+#if defined(SINGULARITY)
+ featureSet(FEATURE_BLACKBOX);
+ masterConfig.blackbox_device = 1;
+ masterConfig.blackbox_rate_num = 1;
+ masterConfig.blackbox_rate_denom = 1;
+
+ masterConfig.batteryConfig.vbatscale = 77;
+
+ featureSet(FEATURE_RX_SERIAL);
+ masterConfig.serialConfig.portConfigs[2].functionMask = FUNCTION_RX_SERIAL;
+#endif
+
// copy first profile into remaining profile
for (i = 1; i < MAX_PROFILE_COUNT; i++) {
memcpy(&masterConfig.profile[i], currentProfile, sizeof(profile_t));
diff --git a/src/main/drivers/pwm_mapping.c b/src/main/drivers/pwm_mapping.c
index b95efed1d..b786ba0ce 100755
--- a/src/main/drivers/pwm_mapping.c
+++ b/src/main/drivers/pwm_mapping.c
@@ -577,6 +577,62 @@ static const uint16_t airPWM[] = {
};
#endif
+#if defined(SINGULARITY)
+static const uint16_t multiPPM[] = {
+ PWM1 | (MAP_TO_PPM_INPUT << 8),
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM5 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM6 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM7 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM8 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM9 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM10 | (MAP_TO_MOTOR_OUTPUT << 8),
+ 0xFFFF
+};
+
+static const uint16_t multiPWM[] = {
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM5 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM6 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM7 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM8 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM9 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM10 | (MAP_TO_MOTOR_OUTPUT << 8),
+ 0xFFFF
+};
+
+static const uint16_t airPPM[] = {
+ PWM1 | (MAP_TO_PPM_INPUT << 8),
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM5 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM6 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM7 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM8 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM9 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM10 | (MAP_TO_SERVO_OUTPUT << 8),
+ 0xFFFF
+};
+
+static const uint16_t airPWM[] = {
+ PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
+ PWM4 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM5 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM6 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM7 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM8 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM9 | (MAP_TO_SERVO_OUTPUT << 8),
+ PWM10 | (MAP_TO_SERVO_OUTPUT << 8),
+ 0xFFFF
+};
+#endif
+
#ifdef SPRACINGF3MINI
static const uint16_t multiPPM[] = {
PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input
@@ -875,6 +931,12 @@ if (init->useBuzzerP6) {
if (timerIndex == PWM7 || timerIndex == PWM8)
type = MAP_TO_SERVO_OUTPUT;
#endif
+
+#if defined(SINGULARITY)
+ // remap PWM6+7 as servos
+ if (timerIndex == PWM6 || timerIndex == PWM7)
+ type = MAP_TO_SERVO_OUTPUT;
+#endif
}
if (init->useChannelForwarding && !init->airplane) {
diff --git a/src/main/drivers/timer.c b/src/main/drivers/timer.c
index f0a8ea960..bc52c6e3c 100755
--- a/src/main/drivers/timer.c
+++ b/src/main/drivers/timer.c
@@ -391,6 +391,31 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
#endif
+#ifdef SINGULARITY
+const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
+ { TIM2, GPIOA, Pin_15, TIM_Channel_1, TIM2_IRQn, 0, Mode_AF_PP, GPIO_PinSource15, GPIO_AF_1}, // PPM/SERIAL RX
+
+ { TIM3, GPIOB, Pin_4, TIM_Channel_1, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource4, GPIO_AF_2}, // PWM1
+ { TIM3, GPIOB, Pin_5, TIM_Channel_2, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource5, GPIO_AF_2}, // PWM2
+ { TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource0, GPIO_AF_2}, // PWM3
+ { TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource1, GPIO_AF_2}, // PWM4
+ { TIM16, GPIOB, Pin_8, TIM_Channel_1, TIM1_UP_TIM16_IRQn, 1, Mode_AF_PP, GPIO_PinSource8, GPIO_AF_1}, // PWM5
+ { TIM17, GPIOB, Pin_9, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 1, Mode_AF_PP, GPIO_PinSource9, GPIO_AF_1}, // PWM6
+
+ { TIM15, GPIOA, Pin_2, TIM_Channel_1, TIM1_BRK_TIM15_IRQn, 1, Mode_AF_PP, GPIO_PinSource2, GPIO_AF_9}, // SOFTSERIAL1 RX (NC)
+ { TIM15, GPIOA, Pin_3, TIM_Channel_2, TIM1_BRK_TIM15_IRQn, 1, Mode_AF_PP, GPIO_PinSource3, GPIO_AF_9}, // SOFTSERIAL1 TX
+
+ { TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 1, Mode_AF_PP, GPIO_PinSource8, GPIO_AF_6}, // LED_STRIP
+};
+
+#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(15) | TIM_N(16) |TIM_N(17))
+
+#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3)
+#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM16 | RCC_APB2Periph_TIM17)
+#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB)
+
+#endif
+
#define USED_TIMER_COUNT BITCOUNT(USED_TIMERS)
#define CC_CHANNELS_PER_TIMER 4 // TIM_Channel_1..4
diff --git a/src/main/sensors/initialisation.c b/src/main/sensors/initialisation.c
index 7e05f9688..ab9b27c89 100755
--- a/src/main/sensors/initialisation.c
+++ b/src/main/sensors/initialisation.c
@@ -182,6 +182,19 @@ const extiConfig_t *selectMPUIntExtiConfig(void)
return &MotolabF3MPU6050Config;
#endif
+#ifdef SINGULARITY
+ static const extiConfig_t singularityMPU6050Config = {
+ .gpioAHBPeripherals = RCC_AHBPeriph_GPIOC,
+ .gpioPort = GPIOC,
+ .gpioPin = Pin_13,
+ .exti_port_source = EXTI_PortSourceGPIOC,
+ .exti_pin_source = EXTI_PinSource13,
+ .exti_line = EXTI_Line13,
+ .exti_irqn = EXTI15_10_IRQn
+ };
+ return &singularityMPU6050Config;
+#endif
+
#ifdef ALIENFLIGHTF3
// MPU_INT output on V1 PA15
static const extiConfig_t alienFlightF3V1MPUIntExtiConfig = {
diff --git a/src/main/target/SINGULARITY/system_stm32f30x.c b/src/main/target/SINGULARITY/system_stm32f30x.c
new file mode 100644
index 000000000..fca696982
--- /dev/null
+++ b/src/main/target/SINGULARITY/system_stm32f30x.c
@@ -0,0 +1,372 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.c
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 28-March-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32F30x devices,
+ * and is generated by the clock configuration tool
+ * stm32f30x_Clock_Configuration_V1.0.0.xls
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f30x.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+ * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ * Supported STM32F30x device
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *----------------------------------------------------------------------------
+ * PLLMUL | 9
+ *-----------------------------------------------------------------------------
+ * PREDIV | 1
+ *-----------------------------------------------------------------------------
+ * USB Clock | ENABLE
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 2
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/** @addtogroup STM32F30x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f30x.h"
+
+uint32_t hse_value = HSE_VALUE;
+
+/**
+ * @}
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/** @addtogroup STM32F30x_System_Private_Defines
+ * @{
+ */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @addtogroup STM32F30x_System_Private_Variables
+ * @{
+ */
+
+ uint32_t SystemCoreClock = 72000000;
+
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings ----------------------------------*/
+ //SetSysClock(); // called from main()
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer and set Flash Latency */
+ FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+ /* PLL configuration */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/src/main/target/SINGULARITY/system_stm32f30x.h b/src/main/target/SINGULARITY/system_stm32f30x.h
new file mode 100644
index 000000000..4f999d305
--- /dev/null
+++ b/src/main/target/SINGULARITY/system_stm32f30x.h
@@ -0,0 +1,76 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.h
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 28-March-2014
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F30X_H
+#define __SYSTEM_STM32F30X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/** @addtogroup STM32F30x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F30X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/main/target/SINGULARITY/target.h b/src/main/target/SINGULARITY/target.h
new file mode 100644
index 000000000..052aaa7c2
--- /dev/null
+++ b/src/main/target/SINGULARITY/target.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of Cleanflight.
+ *
+ * Cleanflight is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Cleanflight is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Cleanflight. If not, see .
+ */
+
+#pragma once
+
+#define TARGET_BOARD_IDENTIFIER "SING"
+
+#define LED0_GPIO GPIOB
+#define LED0_PIN Pin_3
+#define LED0_PERIPHERAL RCC_AHBPeriph_GPIOB
+
+#define BEEP_GPIO GPIOC
+#define BEEP_PIN Pin_15
+#define BEEP_PERIPHERAL RCC_AHBPeriph_GPIOC
+
+#define USABLE_TIMER_CHANNEL_COUNT 10
+
+#define USE_MPU_DATA_READY_SIGNAL
+
+#define GYRO
+#define USE_GYRO_MPU6050
+#define GYRO_MPU6050_ALIGN CW0_DEG_FLIP
+
+#define ACC
+#define USE_ACC_MPU6050
+#define ACC_MPU6050_ALIGN CW0_DEG_FLIP
+
+#define USE_FLASHFS
+#define USE_FLASH_M25P16
+
+#define BEEPER
+#define LED0
+
+#define USE_VCP
+#define USE_USART1 // JST-SH Serial - TX (PA9) RX (PA10)
+#define USE_USART2 // Input - TX (NC) RX (PA15)
+#define USE_USART3 // Solder Pads - TX (PB10) RX (PB11)
+#define USE_SOFTSERIAL1 // Telemetry
+#define SERIAL_PORT_COUNT 5
+
+#define UART1_TX_PIN GPIO_Pin_9
+#define UART1_RX_PIN GPIO_Pin_10
+#define UART1_GPIO GPIOA
+#define UART1_GPIO_AF GPIO_AF_7
+#define UART1_TX_PINSOURCE GPIO_PinSource9
+#define UART1_RX_PINSOURCE GPIO_PinSource10
+
+#define UART2_TX_PIN GPIO_Pin_14 //Not connected
+#define UART2_RX_PIN GPIO_Pin_15
+#define UART2_GPIO GPIOA
+#define UART2_GPIO_AF GPIO_AF_7
+#define UART2_TX_PINSOURCE GPIO_PinSource14
+#define UART2_RX_PINSOURCE GPIO_PinSource15
+
+#define UART3_TX_PIN GPIO_Pin_10
+#define UART3_RX_PIN GPIO_Pin_11
+#define UART3_GPIO_AF GPIO_AF_7
+#define UART3_GPIO GPIOB
+#define UART3_TX_PINSOURCE GPIO_PinSource10
+#define UART3_RX_PINSOURCE GPIO_PinSource11
+
+#define SOFTSERIAL_1_TIMER TIM15
+#define SOFTSERIAL_1_TIMER_RX_HARDWARE 7 //Not connected
+#define SOFTSERIAL_1_TIMER_TX_HARDWARE 8
+
+#define USE_I2C
+#define I2C_DEVICE (I2CDEV_1) // PB6/SCL, PB7/SDA
+
+#define USE_SPI
+#define USE_SPI_DEVICE_2 // PB12,13,14,15 on AF5
+
+#define M25P16_CS_GPIO GPIOB
+#define M25P16_CS_PIN GPIO_Pin_12
+#define M25P16_SPI_INSTANCE SPI2
+
+#define USE_ADC
+#define BOARD_HAS_VOLTAGE_DIVIDER
+
+#define ADC_INSTANCE ADC2
+#define ADC_DMA_CHANNEL DMA2_Channel1
+#define ADC_AHB_PERIPHERAL RCC_AHBPeriph_DMA2
+
+#define VBAT_ADC_GPIO GPIOB
+#define VBAT_ADC_GPIO_PIN GPIO_Pin_2
+#define VBAT_ADC_CHANNEL ADC_Channel_12
+
+#define LED_STRIP
+#define LED_STRIP_TIMER TIM1
+
+#define USE_LED_STRIP_ON_DMA1_CHANNEL2
+#define WS2811_GPIO GPIOA
+#define WS2811_GPIO_AHB_PERIPHERAL RCC_AHBPeriph_GPIOA
+#define WS2811_GPIO_AF GPIO_AF_6
+#define WS2811_PIN GPIO_Pin_8
+#define WS2811_PIN_SOURCE GPIO_PinSource8
+#define WS2811_TIMER TIM1
+#define WS2811_TIMER_APB2_PERIPHERAL RCC_APB2Periph_TIM1
+#define WS2811_DMA_CHANNEL DMA1_Channel2
+#define WS2811_IRQ DMA1_Channel2_IRQn
+#define WS2811_DMA_TC_FLAG DMA1_FLAG_TC2
+#define WS2811_DMA_HANDLER_IDENTIFER DMA1_CH2_HANDLER
+
+#define AUTOTUNE
+#define BLACKBOX
+#define TELEMETRY
+#define SERIAL_RX
+#define GPS
+#define USE_SERVOS
+#define USE_CLI
+
+#define SPEKTRUM_BIND
+// USART2, PA15
+#define BIND_PORT GPIOA
+#define BIND_PIN Pin_15
+
+#define USE_SERIAL_4WAY_BLHELI_INTERFACE
+