Added generated timer definitions for STM32F7X2 universal target.
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mikeller
parent
717444175c
commit
16a96f7318
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@ -28,32 +28,94 @@
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#include "drivers/timer_def.h"
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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// Auto-generated from 'timer_def.h'
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//PORTA
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DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM12, CH2, PB15, TIM_USE_PWM | TIM_USE_PPM, 0, 0),
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DEF_TIM(TIM8, CH1, PC6, TIM_USE_PWM, 0, 0),
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DEF_TIM(TIM8, CH2, PC7, TIM_USE_PWM, 0, 0),
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DEF_TIM(TIM8, CH4, PC9, TIM_USE_PWM, 0, 0),
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DEF_TIM(TIM8, CH3, PC8, TIM_USE_PWM, 0, 0),
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DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 0, 0),
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DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 0, 1),
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DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 0, 0),
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DEF_TIM(TIM4, CH4, PB9, TIM_USE_MOTOR, 0, 0),
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DEF_TIM(TIM9, CH2, PE6, TIM_USE_MOTOR, 0, 0),
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DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 0, 0),
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//11
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DEF_TIM(TIM10, CH1, PB8, 0, 0, 0),
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DEF_TIM(TIM5, CH4, PA3, 0, 0, 0),
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DEF_TIM(TIM9, CH2, PA3, 0, 0, 0),
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DEF_TIM(TIM11, CH1, PB9, 0, 0, 0),
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DEF_TIM(TIM1, CH1N, PB13, 0, 0, 0),
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DEF_TIM(TIM1, CH2N, PB14, 0, 0, 0),
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DEF_TIM(TIM8, CH2N, PB14, 0, 0, 0),
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DEF_TIM(TIM12, CH1, PB14, 0, 0, 0),
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DEF_TIM(TIM1, CH3N, PB15, 0, 0, 0),
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DEF_TIM(TIM8, CH3N, PB15, 0, 0, 0),
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DEF_TIM(TIM3, CH1, PC6, 0, 0, 0),
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DEF_TIM(TIM3, CH2, PC7, 0, 0, 0),
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DEF_TIM(TIM3, CH4, PC9, 0, 0, 0),
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DEF_TIM(TIM3, CH3, PC8, 0, 0, 0),
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DEF_TIM(TIM9, CH1, PA2, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM9, CH2, PA3, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0),
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//PORTB
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DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM10, CH1, PB8, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM11, CH1, PB9, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH2N, PB14, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH3N, PB15, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0),
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//PORTC
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DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0),
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//PORTD
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DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0),
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//PORTE
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DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM9, CH1, PE5, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM9, CH2, PE6, TIM_USE_ANY, 0, 0),
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//PORTF
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DEF_TIM(TIM10, CH1, PF6, TIM_USE_ANY, 0, 0),
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DEF_TIM(TIM11, CH1, PF7, TIM_USE_ANY, 0, 0),
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};
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@ -92,6 +92,6 @@
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#define TARGET_IO_PORTE 0xffff
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#define TARGET_IO_PORTF 0xffff
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#define USABLE_TIMER_CHANNEL_COUNT 25
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#define USABLE_TIMER_CHANNEL_COUNT 70
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#define USE_TIMER_MGMT
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